QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 40

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

2.2
2.2.1
40
DDR2 DRAM Interface
DDR2 SDRAM Channel A Interface
SA_DQ[63:0]
SA_DM[7:0]
SA_DQS[7:0]
SA_DQS[7:0]#
SA_MA[13:0]
SA_BS[2:0]
SA_RAS#
SA_CAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#
Signal Name
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
SSTL1.8
Type
I/O
I/O
I/O
2x
2X
2x
2x
O
O
O
O
O
O
O
I
Data Bus:
DDR2 Channel A data signal interface to the SDRAM data
bus.
Data Mask:
These signals are used to mask individual bytes of data in
the case of a partial write, and to interrupt burst writes.
When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one
SA_DM[7:0] for every data byte lane.
Data Strobes:
SA_DQS[7:0] and its complement signal group make up
a differential strobe pair. The data is captured at the
crossing point of SA_DQS[7:0] and its SA_DQS[7:0]#
during read and write transactions.
Data Strobe Complements:
These are the complementary strobe signals.
Memory Address:
These signals are used to provide the multiplexed row
and column address to the SDRAM.
Note: SA_MA13 is for support of 1-Gb devices.
Bank Select:
These signals define which banks are selected within each
SDRAM rank.
RAS Control Signal:
Used with SA_CAS# and SA_WE# (along with SM_CS#)
to define the SDRAM commands.
CAS Control Signal:
Used with SA_RAS# and SA_WE# (along with SM_CS#)
to define the SDRAM commands.
Write Enable Control Signal:
Used with SA_RAS# and SA_CAS# (along with SM_CS#)
to define the SDRAM commands.
Clock Input:
Used to emulate source-synch clocking for reads.
Connects internally to SA_RCVENOUT#.
Leave as No Connect.
Clock Output:
Used to emulate source-synch clocking for reads.
Connects internally to SA_RCVENIN#.
Leave as No Connect.
Description
Signal Description
Datasheet