QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 131

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
Datasheet
Below is the validation matrix for tCL, tRCD and tRP in table format.
400 MHz
533 MHz
667 MHz
6:4
2:0
Bit
3
Access
R/W
R/W
RO
(CLK Periods)
tCL
3
4
5
Default
Value
010b
010b
0b
(CLK Periods)
DRAM RASB to CASB Delay (tRCD):
This bit controls the number of clocks inserted between a row
activate command and a read or write command to that row.
Note: The timings validated by Intel for each DDR2 frequency
are indicated above.
Reserved
DRAM RASB Precharge (tRP):
This bit controls the number of clocks that are inserted between
a row precharge command and an activate command to the
same rank.
Encoding
Encoding
101-111
110-111
tRCD
000
001
010
011
100
000
001
010
011
100
101
3
4
5
(Sheet 3 of 3)
2 DRAM Clocks
3 DRAM Clocks (Validated for DDR2 400 MHz)
4 DRAM Clocks (Validated for DDR2 533 MHz)
5 DRAM Clocks (Validated for DDR2 667 MHz)
6 DRAM Clocks
Reserved
2 DRAM Clocks
3 DRAM Clocks (Validated for DDR2 400 MHz)
4 DRAM Clocks (Validated for DDR2 533 MHz)
5 DRAM Clocks (Validated for DDR2 667 MHz)
6 DRAM Clocks
7 DRAM Clocks
Reserved
(CLK Periods)
tRP
3
4
5
Description
tRCD
tRP
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