QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 301

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Internal Graphics Device 2 Configuration Register (D2:F0-F1)
8.2.3
Datasheet
PCICMD2 - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD register in the IGD disables the IGD PCI-compliant master
accesses to main memory.
15:11
10:10
Bit
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00h
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Reserved
Reserved
Fast Back-to-Back (FB2B):
Not Implemented. Hardwired to 0.
SERR Enable (SERRE):
Not Implemented. Hardwired to 0.
Address/Data Stepping Enable (ADSTEP):
Not Implemented. Hardwired to 0.
Parity Error Enable (PERRE):
Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not
corrupt programs or data in system memory or hard drives, the
IGD ignores any parity error that it detects and continues with
normal operation.
VGA Palette Snoop Enable (VGASNOOP):
This bit is hardwired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE):
Hardwired to 0. The IGD does not support memory write and
invalidate commands.
Special Cycle Enable (SCE):
This bit is hardwired to 0. The IGD ignores Special cycles.
Bus Master Enable (BME):
Set to 1 to enable the IGD to function as a PCI-compliant master.
Set to 0 to disable IGD bus mastering.
Memory Access Enable (MAE):
This bit controls the IGD's response to memory space accesses.
I/O Access Enable (IOAE):
This bit controls the IGD's response to I/O space accesses.
0: Disable
1: Enable
0: Disable
1: Enable
0/2/1/PCI
4-5h
0000h
R/W; RO
16 bits
Description
301