QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 337

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Functional Description
10
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
Datasheet
Functional Description
Host Interface
FSB Source Synchronous Transfers
The (G)MCH supports the Intel Core Duo and Intel Core Solo processor subset of the
Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous
transfer is used for the address and data signals. The address signals are double
pumped and a new address can be generated every other bus clock. At 133-MHz and
166-MHz bus clock the address signals run at 266 and 333 MT/s for a maximum
address queue rate of 66 M and 83 M addresses/sec. The data is quad pumped and an
entire 64-B cache line can be transferred in two bus clocks. At 133-MHz and 166-MHz
bus clock, the data signals run at 533 MHz and 667 MHz for a maximum bandwidth of
4.3 GB/s and 5.3 GB/s respectively.
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
FSB OOQ Depth
The (G)MCH supports only one outstanding deferred transaction on the FSB.
FSB GTL+ Termination
The (G)MCH integrates GTL+ termination resistors on die.
FSB Dynamic Bus Inversion
The (G)MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving
data from the CPU. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the (G)MCH. HDINV[3:0]# indicate if the corresponding 16 bits of data
are inverted on the bus for each quad pumped data phase:
Whenever the processor or the (G)MCH drives data, each 16-bit segment is analyzed.
If more than 8 of the 16 signals would normally be driven low on the bus the
corresponding HDINV# signal will be asserted and the data will be inverted prior to
being driven on the bus. Whenever the CPU or the (G)MCH receives data it monitors
HDINV[3:0]# to determine if the corresponding data segment should be inverted.
HDINV[0]#
HDINV[1]#
HDINV[2]#
HDINV[3]#
HDINV[3:0]#
HD[15:0]#
HD[31:16]#
HD[47:32]#
HD[63:48]#
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