QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 248

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

7.1.29
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MA - Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:2
6:4
3:1
1:0
Bit
Bit
0
Access
Access
R/W
R/W
R/W
RO
RO
00000000h
Default
Value
Default
000b
000b
Value
0b
00b
Multiple Message Enable (MME):
System software programs this field to indicate the actual number
of messages allocated to this device. This number will be equal to
or less than the number actually requested.
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC):
System software reads this field to determine the number of
messages being requested by this device.
MSI Enable (MSIEN):
Controls the ability of this device to generate MSIs.
messages. INTA will not be generated and INTA Status
(PCISTS1[3]) will not be set.
All of the following are reserved in this implementation:
0:MSI will not be generated.
1:MSI will be generated when we receive PME or HotPlug
Message Address (MA):
Used by system software to assign an MSI address to the
device. The device handles an MSI by writing the padded
contents of the MD register to this address.
Force Dword Align (FDWA):
Hardwired to 0 so that addresses assigned by system software
are always aligned on a dword address boundary.
Value:Number of Messages Requested
000: 1
001: 2
010: 4
011: 8
100: 16
101: 32
110: Reserved
111: Reserved
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/PCI
94-97h
00000000h
R/W; RO
32 bits
Description
Description
Datasheet