QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 277

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Internal Graphics Device 2 Configuration Register (D2:F0-F1)
8.1.4
Datasheet
PCISTS2 - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of a PCI-compliant
master abort and PCI-compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
10:9
Bit
15
14
13
12
11
8
7
6
5
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
1b
0b
0b
Detected Parity Error (DPE):
Since the IGD does not detect parity, this bit is always hardwired
to 0.
Signaled System Error (SSE):
The IGD never asserts SERR#, therefore this bit is hardwired to
0.
Received Master Abort Status (RMAS):
The IGD never gets a Master Abort, therefore this bit is hardwired
to 0.
Received Target Abort Status (RTAS):
The IGD never gets a Target Abort, therefore this bit is hardwired
to 0.
Signaled Target Abort Status (STAS):
Hardwired to 0. The IGD does not use target abort semantics.
DEVSEL Timing (DEVT):
N/A. These bits are hardwired to 00.
Master Data Parity Error Detected (DPD):
Since Parity Error Response is hardwired to disabled (and the IGD
does not do any parity detection), this bit is hardwired to 0.
Fast Back-to-Back (FB2B):
Hardwired to 1. The IGD accepts fast back-to-back when the
transactions are not to the same agent.
User Defined Format (UDF):
Hardwired to 0.
66-MHz PCI Capable (66C):
N/A - Hardwired to 0.
0/2/0/PCI
6-7h
0090h
R/WC; RO
16 bits
Description
277