QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 145

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.39
Datasheet
C1GTEW - Channel 1 (G)MCH Throttling Event Weights
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains programmable Event weights that are input into the averaging
filter. Each Event weight is a normalized 8-bit value that the BIOS must program. The
BIOS must account for burst length considerations. It is also possible for BIOS to take
into account loading variations caused by different memory types and population of
ranks.
31:24
23:16
15:8
7:0
Bit
Access
R/W/L
R/W/L
R/W/L
R/W/L
Default
Value
00h
00h
00h
00h
Read Weight:
This value is input to the filter if in a given clock there is a valid
read command being issued on the memory bus.
Write Weight:
This value is input to the filter if in a given clock there is a valid
write command being issued on the memory bus.
Command Weight:
This value is input to the filter if in a given clock there is a valid
command other than a read or a write being issued on the
memory bus.
Idle Weight:
This value is input to the filter if in a given clock there is no
command being issued on the memory bus.
0/0/0/MCHBAR
1C0-1C3h
00000000h
R/W/L
32 bits
Description
145