QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 155
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
- Current page: 155 of 482
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Device 0 Memory Mapped I/O Register
6.2.62
6.2.63
6.2.64
6.2.65
Datasheet
C1WL0REOST - Channel 1 WL0 RCVENOUT Slave Timing
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]).
C1WL1REOST - Channel 1 WL1 RCVENOUT Slave Timing
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]).
C1WL2REOST - Channel 1 WL2 RCVENOUT Slave Timing
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]).
C1WL3REOST - Channel 1 WL3 RCVENOUT Slave Timing
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]).
0/0/0/MCHBAR
3C0h
00h
R/W/L; RO
8 bits
0/0/0/MCHBAR
3C1h
00h
R/W/L; RO
8 bits
0/0/0/MCHBAR
3C2h
00h
R/W/L; RO
8 bits
0/0/0/MCHBAR
3C3h
00h
R/W/L; RO
8 bits
155
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