QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 130

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

130
15:10
9:8
Bit
7
Access
R/W
R/W
RO
Default
Value
1Ch
01b
0b
Refresh Cycle Time (tRFC):
Refresh cycle time is measured from a Refresh command (REF)
until the first Activate command (ACT) to the same rank,
required to perform a read or write.
For DDR2, tRFC needs to follow the values recommended in the
table below:
CASB Latency (tCL):
This value is programmable on DDR2 DIMMs. The value
programmed here must match the CAS Latency of every DDR2
DIMM in the system.
Note: The timings validated by Intel for each DDR2 frequency
are indicated above.
Reserved
Active/Refresh
command time
Parameter
Refresh to
DDR2-400
DDR2-533
DDR2-677
Encoding
00
01
10
11
(Sheet 2 of 3)
5 (Validated for DDR2 667 MHz)
4 (Validated for DDR2 533 MHz)
3 (Validated for DDR2 400 MHz)
6
Symbol
tRFC
Description
5
4
3
Device 0 Memory Mapped I/O Register
DDR2 CL
256 Mb
75
15
20
25
512 Mb
105
21
28
35
Datasheet
127.5
1 Gb
26
34
43