QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 231
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
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PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.5
Datasheet
RID1 - Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the revision number of the (G)MCH Device 1. These bits are read
only and writes to this register have no effect.
2:0
7:0
Bit
Bit
8
7
6
5
4
3
Access
Access
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
000b
00h
0b
0b
0b
0b
1b
0b
Master Data Parity Error (PMDPE):
Because the primary side of the PEG's virtual PCI-to-PCI bridge is
integrated with the MCH functionality there is no scenario where
this bit will get set. Because hardware will never set this bit, it is
impossible for software to have an opportunity to clear this bit or
otherwise test that it is implemented. The PCI Local Bus
Specification defines it as a R/WC, but for our implementation an
RO definition behaves the same way and will meet all Microsoft
testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
Fast Back-to-Back (FB2B):
Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60 MHz Capability (CAP66):
Not Applicable or Implemented. Hardwired to 0.
Capabilities List (CAPL):
Indicates that a capabilities list is present. Hardwired to 1.
INTA Status (INTAS):
Indicates that an interrupt message is pending internally to the
device. Only PME and Hot Plug sources feed into this status bit
(not PCI INTA-INTD assert and deassert messages). The INTA
Assertion Disable bit, PCICMD1[10], has no effect on this bit.
Note that INTA emulation interrupts received across the link are
not reflected in this bit.
Reserved
Revision Identification Number (RID1):
This is an 8-bit value that indicates the revision identification
number for the (G)MCH Device 0. For the A-0 Stepping, this
value is 00h.
0/1/0/PCI
08h
00h
RO
8 bits
(Sheet 2 of 2)
Description
Description
231
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