QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 317

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Internal Graphics Device 2 Configuration Register (D2:F0-F1)
8.4.1
8.4.2
Note:
Datasheet
Index - MMIO Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
MMIO_INDEX: A 32-bit IO write to this port loads the offset of the MMIO register that
needs to be accessed. An IO Read returns the current value of this register. An 8-/16-
bit IO write to this register is completed by the (G)MCH but does not update this
register. This mechanism to access internal graphics MMIO registers must not be used
to access VGA IO registers which are mapped through the MMIO space. VGA registers
must be accessed directly through the dedicated VGA IO ports.
Data - MMIO Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
location pointed to by the MMIO-index register. A 32-bit IO read to this port is re-
directed to the MMIO register address pointed to by the MMIO-index register regardless
of the target selection in MMIO_INDEX(1:0). 8- or 16-bit IO writes are completed by
the (G)MCH and may have un-intended side effects, hence must not be used to access
the data port. 8- or 16-bit IO reads are completed normally.
If the target field in MMIO Index selects “GTT”, Reads to MMIO data return 0’s and not
the value programmed in the GTT memory corresponding to the offset programmed in
MMIO index.
MMIO_DATA: A 32-bit IO write to this port is re-directed to the MMIO register/GTT
31:2
31:0
1:0
Bit
Bit
Access
Access
R/W
R/W
R/W
00000000h
00000000h
Default
Default
Value
Value
00b
Reserved
Target:
00:MMIO Registers
Others:Reserved
MMIO Data Window
§
0/2/0/PCI IO
IOBAR + 0h
00000000h
R/W
32 bits
0/2/0/PCI IO
IOBAR + 4h
00000000h
R/W
32 bits
Description
Description
317