QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 328

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

9.3.1
Note:
9.3.2
9.3.3
9.3.4
328
APIC Configuration Space (FEC0_0000h-FECF_FFFFh)
This range is reserved for APIC configuration space which includes the default I/O APIC
configuration space from FEC0_0000h to FEC7_0FFFh. The default Local (CPU) APIC
configuration space goes from FEC8_0000h to FECF_FFFFh.
CPU accesses to the Local APIC configuration space do not result in external bus
activity since the Local APIC configuration space is internal to the CPU. However, an
MTRR must be programmed to make the Local APIC range uncacheable (UC). The Local
APIC base address in each CPU should be relocated to the FEC0_0000h (4 GB-20 MB)
to FECF_FFFFh range so that one MTRR can be programmed to 64 KB for the Local and
I/O APICs. The I/O APIC(s) usually reside in the ICH portion of the chip set or as a
stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/
O APIC will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h
where x is I/O APIC unit number 0 through F(hex). This address range will normally be
mapped to DMI.
There is no provision to support an I/O APIC device on PCI Express.
HSEG (FEDA_0000h-FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window
to SMM memory. It is sometimes called the High SMM memory space. SMM-mode CPU
accesses to the optionally enabled HSEG are remapped to 000A_0000h - 000B_FFFFh.
Non-SMM mode CPU accesses to enabled HSEG are considered invalid and are
terminated immediately on the FSB. The exceptions to this rule are Non-SMM mode
Write Back cycles which are remapped to SMM space to maintain cache coherency. PCI
Express and DMI originated cycles to enabled SMM space are not allowed. Physical
DRAM behind the HSEG transaction address is not remapped and is not accessible. All
Cacheline writes with WB attribute or implicit write backs to the HSEG range are
completed to DRAM like an SMM cycle.
FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any
device on PCI Express, Internal Graphics, or DMI may issue a Memory Write to
0FEEx_xxxxh. The (G)MCH will forward this Memory Write along with the data to the
FSB as an Interrupt Message Transaction. The (G)MCH terminates the FSB transaction
by providing the response and asserting HTRDY#. This Memory Write cycle does not go
to DRAM.
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The CPU begins execution from the High BIOS after reset. This region is
mapped to DMI so that the upper subset of this region aliases to the 16-MB–256-KB
range. The actual address space required for the BIOS is less than 2 MB but the
minimum CPU MTRR range for this region is 2 MB so that full 2 MB must be considered.
System Address Map
Datasheet