AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 681

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

41.12.10 Spurious counter overflow in Up/Down Mode
41.13 TWI
41.13.1
41.13.2
41.13.3
41.13.4
41.13.5
1768I–ATARM–09-Jul-09
Disabling Does not Operate Correctly
NACK Status Bit Lost
Possible Receive Holding Register Corruption
Clock Divider
Software reset
None.
When the field WAVESEL in TC_CMR is at value 0x1 or 0x3 and when the counter reaches the
value 0xFFFF, it inverts its sense and decrements to 0xFFFE. At the same time, the OVF bit in
TC_SR is set.
Problem Fix/Workaround
None.
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with
the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register
(TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts
must be disabled before disabling the TWI.
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as
long as transmission is not completed.
Note:
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
Problem Fix/Workaround
The user must be sure that received data is read before transmitting any new data.
The value of CLDIV x 2
must be less than or equal to 8191.
Problem Fix/Workaround
None.
When a software reset is performed during a frame and when TWCK is low, it is impossible to
initiate a new transfer in READ or WRITE mode.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the
TWI_SR.
CKDIV
must be less than or equal to 8191; the value of CHDIV x 2
AT91RM9200
CKDIV
681