AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 117
AT91RM9200-QI-002
Manufacturer Part Number
AT91RM9200-QI-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-QI-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
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15. AT91RM9200 Reset Controller
15.1
15.1.1
15.1.1.1
1768I–ATARM–09-Jul-09
Overview
Reset Conditions
NRST Conditions
This chapter describes the AT91RM9200 reset signals and how to use them in order to assure
correct operation of the device.
The AT91RM9200 has two reset input lines called NRST and NTRST. Each line provides,
respectively:
The NRST signal must be considered as the System Reset signal and the reader must take care
when designing the logic to drive this reset signal. NTRST is typically used by the hardware
debug interface which uses the In-Circuit Emulator unit and Initializes it without affecting the nor-
mal operation of the ARM
Both NRST and NTRST are active low signals that asynchronously reset the logic in the
AT91RM92000.
NRST is the active low reset input. When power is first applied to the system, a power-on reset
(also denominated as “cold” reset) must be applied to the AT91RM9200. During this transient
state, it is mandatory to hold the reset signal low long enough for the power supply to reach a
working nominal level and for the oscillator to reach a stable operating frequency. Typically,
these features are provided by every power supply supervisor which, under a threshold voltage
limit, the electrical environment is considered as not nominal. Power-up is not the only event to
be considered as power-down or a brownout are also occurrences that assert the NRST signal.
The threshold voltage must be selected according to the minimum operating voltage of the
AT91RM9200 power supply lines marked as VDD in
acteristics” on page 632.)
The choice of the reset holding delay depends on the start-up time of the low frequency oscilla-
tor as shown below in
page 633.)
Figure 15-1. Cold Reset and Oscillator Start-up relationship
• Initialization of the User Interface registers (defined in the user interface of each peripheral)
• Initialization of the embedded ICE TAP controller.
XIN32
NRST
V
and:
DD
– Sample the signals needed at bootup
– Compel the processor to fetch the next instruction at address zero.
(1)
V
DD(min)
Oscillator Stabilization
after Power-Up
Figure
®
processor. This line shall also be driven by an on board logic.
15-1.
(See Section 37.4.1 ”32 kHz Oscillator Characteristics” on
Figure
15-1.
(See Section 37.2 ”DC Char-
AT91RM9200
117
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