AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 676

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

41.8
41.8.1
41.8.2
41.8.3
41.8.4
41.8.5
41.9
41.9.1
676
SDRAMC
SMC
AT91RM9200
SDRC_IMR can be written
No wrap-around for SDRAM devices with two internal banks
No t
Some devices are not supported
Interrupt Disable Register
Address Bus continuously active
RC
after refresh when low-power mode is enabled
The Interrupt Mask Register in the SDRAM Controller is not read-only. Thus, writing to it modi-
fies the contents instead of having no effect.
Problem Fix/Workaround
None.
In the case of SDRAM devices featuring two internal banks, when the physical address is higher
than the memory size, the SDRAM controller does not wrap around. It activates virtual bank
numbers three or four.
Problem Fix/Workaround
None.
When low-power mode is enabled and after a refresh command is sent to the SDRAM, the
SDRAM Controller enters low-power mode by asserting SDCKE low. The t
Auto-refresh and Low-power mode is not respected. As SDCKE is low, the INHIBIT and NOP
commands are not sent to the SDRAM.
For the moment this warning has no effect on the correct functionality of the SDRAM.
Problem Fix/Workaround
None.
The SDRAM controller does not support the following devices in 32-bit mode:
Problem Fix/Workaround
None.
Writing 0 to the Interrupt Enable Register or to the Interrupt Disable Register modifies the value
of Interrupt Mask Register.
Problem Fix/Workaround
None.
The address bus is continuously driven with the address of the current access, even if it is an
internal one.
Problem Fix/Workaround
• 128 Mbit device: 32M*4bits: 4 banks/12 rows/11 columns
• 256 Mbit device: 64M*4bits: 4 banks/13 rows/11 columns
RC
1768I–ATARM–09-Jul-09
timing between