AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet
AT91RM9200-QI-002
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AT91RM9200-QI-002 Summary of contents
Page 1
... RS485 Support, IrDA Up To 115 Kbps – Full Modem Control Lines on USART1 • Master/Slave Serial Peripheral Interface (SPI) – 16-bit Programmable Data Length, 4 External Peripheral Chip Selects ® ® Thumb Processor ™ (256-ball BGA Package ® ARM920T-based Microcontroller AT91RM9200 Rev. 1768I-ATARM–09-Jul-09 ...
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... Flash Card, infrared and Smart Card applications. To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints ...
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... Block Diagram Bold arrows ( Figure 2-1. AT91RM9200 Block Diagram Reset TST0-TST1 and NRST Test JTAGSEL TDI JTAG TDO Scan TMS TCK NTRST FIQ IRQ0-IRQ6 PCK0-PCK3 PLLRCB PLLB PLLRCA PLLA XIN OSC XOUT XIN32 OSC XOUT32 DRXD DTXD PIOA/PIOB/PIOC/PIOD DDM DDP MCCK ...
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... JTAG Selection TSYNC Trace Synchronization Signal TCLK Trace Clock TPS0 - TPS2 Trace ARM Pipeline Status TPK0 - TPK15 Trace Packet Port NRST Microcontroller Reset TST0 - TST1 Test Mode Select AT91RM9200 4 Active Type Power Power Power Power Power Power Ground Ground Ground Clocks, Oscillators and PLLs ...
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... Output Input Output EBI for CompactFlash Support Output Output Output Output Output Output Output AT91RM9200 Active Level Comments Debug Receive Data Debug Transmit Data Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset 0 at reset ...
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... Receive Data RTS0 - RTS3 Ready To Send CTS0 - CTS3 Clear To Send DSR1 Data Set Ready DTR1 Data Terminal Ready DCD1 Data Carrier Detect RI1 Ring Indicator AT91RM9200 6 Type EBI for NAND Flash/SmartMedia Support Output Output Output SDRAM Controller Output Output Output Output Output ...
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... I/O Output Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter Input I/O I/O AT91RM9200 Active Level Comments RMII only MII only MII only ETX0 - ETX1 only in RMII MII only MII only RMII only ERX0 - ERX1 only in RMII MII only ...
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... Parallel I/O Controller D • ETM • a second USB Host transceiver, opening the Hub capabilities of the embedded USB Host. 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91RM9200 Mechanical Characteris- tics” of the product datasheet. Figure 4-1. AT91RM9200 8 SPI Two-Wire Interface ™ ...
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... PQFP Package Pinout Table 4-1. AT91RM9200 Pinout for 208-pin PQFP Package Pin Number Signal Name 1 PC24 2 PC25 3 PC26 4 PC27 5 PC28 6 PC29 7 VDDIOM 8 GND 9 PC30 10 PC31 11 PC10 12 PC11 13 PC12 14 PC13 15 PC14 16 PC15 17 PC0 18 PC1 19 VDDCORE 20 GND 21 PC2 22 PC3 23 PC4 24 PC5 ...
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... A21 160 A22 Note: 1. Shaded cells define the pins powered by VDDIOM. 4.3 256-ball BGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91RM9200 Mechanical Characteris- tics” of the product datasheet. Figure 4-2. AT91RM9200 10 Pin Pin Number Signal Name ...
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... BGA Package Pinout Table 4-2. AT91RM9200 Pinout for 256-ball BGA Package Pin Signal Name A1 TDI A2 JTAGSEL A3 PB20 A4 PB17 A5 PD11 A6 PD8 A7 VDDIOP A8 PB9 A9 PB4 A10 PA31/BMS A11 VDDIOP A12 PA23 A13 PA19 A14 GND A15 PA14 A16 VDDIOP A17 PA13 ...
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... Table 4-2. AT91RM9200 Pinout for 256-ball BGA Package (Continued) Pin Signal Name L1 GND L2 HDPB L3 HDMB GND L6 VDDIOP L12 PC10 L13 PC15 L14 PC2 L15 PC3 L16 VDDCORE L17 PLLRCA M1 VDDIOM M2 GND A1/NBS2/NWR2 M5 A10 GND M9 NCS1/SDCS M11 D4 M12 GND M13 PC13 M14 ...
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... Ground pins are common to all power supplies, except VDDPLL and VDDOSC pins. For these pins, GNDPLL and GNDOSC are provided, respectively. 5.2 Power Consumption The AT91RM9200 consumes about 500 µA of static current on VDDCORE at 25⋅ C. For dynamic power consumption, the AT91RM9200 consumes a maximum VDDCORE at maximum speed in typical conditions (1.8V, 25⋅ C), processor running full-performance algorithm. ...
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... Access permission for large pages and small pages can be specified separately for – 16 embedded domains – 64 Entry Instruction TLB and 64 Entry Data TLB 8-, 16-, 32-bit Data Bus for Instructions and Data 7.2 Debug and Test • Integrated EmbeddedICE AT91RM9200 14 ™ -based on ARM Architecture v4T each quarter of the pages 1768I–ATARM–09-Jul-09 ...
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... Memory Controller • Programmable Bus Arbiter handling four Masters – Internal Bus is shared by ARM920T, PDC, USB Host Port and Ethernet MAC – Each Master can be assigned a priority between 0 and 7 1768I–ATARM–09-Jul-09 ™ Rev2a ® connected on SPI NPCS0 Masters AT91RM9200 15 ...
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... Source, Type and all parameters of the access leading to an abort are saved • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap command – Provides remapping of an internal SRAM in place of the boot NVM AT91RM9200 16 1768I–ATARM–09-Jul-09 ...
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... Memories Figure 8-1. AT91RM9200 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 / BFC 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1 / SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes ...
Page 18
... Remap, the SRAM is also available at address 0x0. 8.1.1.2 Internal ROM The AT91RM9200 integrates a 128-Kbyte Internal ROM. At any time, the ROM is mapped at address 0x10 0000 also accessible at address 0x0 after reset and before the Remap Com- mand if the BMS is tied high during reset. ...
Page 19
... Embeds and controls: – One Main Oscillator and One Slow Clock Oscillator (32.768Hz) – Two Phase Locked Loops (PLLs) and Dividers – Clock Prescalers • Provides: – the Processor Clock PCK 1768I–ATARM–09-Jul-09 Figure 8-1 on page interrupts External Sources AT91RM9200 17. 19 ...
Page 20
... Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time AT91RM9200 20 USB Device Port Generator peripherals 1768I–ATARM–09-Jul-09 ...
Page 21
... A complete memory map is presented in 10.2 Peripheral Identifiers The AT91RM9200 embeds a wide range of peripherals. tifiers of the AT91RM9200. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. ...
Page 22
... Peripheral Multiplexing on PIO Lines The AT91RM9200 features four PIO controllers: • PIOA and PIOB, multiplexing I/O lines of the peripheral set • PIOC, multiplexing the data bus bits and several External Bus Interface control signals. Using PIOC pins increases the number of general-purpose I/O lines available but prevents 32-bit memory access • ...
Page 23
... TCLK1 I/O TCLK2 I/O IRQ6 I/O TIOA0 I/O TIOB0 I/O TIOA1 I/O TIOB1 I/O TIOA2 I/O TIOB2 I/O IRQ3 I/O PCK1 I/O IRQ2 I/O IRQ1 I/O TCLK3 I/O TCLK4 I/O TCLK5 I/O CTS2 I/O RTS2 I/O AT91RM9200 Application Usage Function Comments 23 ...
Page 24
... DTR1 PB20 TXD1 PB21 RXD1 PB22 SCK1 PB23 DCD1 PB24 CTS1 PB25 DSR1 PB26 RTS1 PB27 PCK0 PB28 FIQ PB29 IRQ0 AT91RM9200 24 Reset Peripheral B State RTS3 I/O CTS3 I/O SCK3 I/O MCDA1 I/O MCDA2 I/O MCDA3 I/O TIOA3 I/O TIOB3 I/O ...
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... Reset Peripheral B State I/O I/O I/O I/O I/O I/O I/O A23 A24 A25 NCS4 NCS5 NCS6 NCS7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AT91RM9200 Application Usage Function Comments 25 ...
Page 26
... The PIO Controller D multiplexes pure output signals on peripheral A connections, in particular from the EMAC MII inter- face and the ETM Port on the peripheral B connections. The PIO Controller D is available only in the 256-ball BGA package option of the AT91RM9200. Table 10-5. Multiplexing on PIO Controller D ...
Page 27
... External memory mapping, 512-Mbyte address space • Chip Select Lines • 16-bit Data Bus • Remap of Boot Memory • Multiple Access Modes supported – Byte Write or Byte Select Lines – Two different Read Protocols for each Memory Bank • Multiple device adaptability 1768I–ATARM–09-Jul-09 AT91RM9200 27 ...
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... Adaptability to different device access protocols and bus interfaces – Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled – Multiplexed or separate address and data buses – Continuous Burst and Page Mode Accesses supported AT91RM9200 28 Address Advance 1768I–ATARM–09-Jul-09 ...
Page 29
... Ping-pong mode (two memory banks) for isochronous and bulk endpoints • Six general-purpose endpoints – Endpoint 0, Endpoint 3: 8 bytes, no ping-pong mode – Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode – Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode 10.13 Ethernet MAC • Compatibility with IEEE Standard 802.3 1768I–ATARM–09-Jul-09 AT91RM9200 29 ...
Page 30
... Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection AT91RM9200 30 peripherals Sensors and data per chip select ...
Page 31
... The USART describes features allowing management of the Modem Signals DTR, DSR, DCD and RI. For details, see In the AT91RM9200, only the USART1 implements these signals, named DTR1, DSR1, DCD1 and RI1. The USART0, USART2 and USART3 do not implement all the modem signals. Only RTS and CTS (RTS0 and CTS0, RTS2 and CTS2, RTS3 and CTS3, respectively) are implemented in these USARTs for other features ...
Page 32
... Two global registers that act on all three TC Channels • The Timer Counter are described with five generic clock inputs, TIMER_CLOCK1 to TIMER_CLOCK5. In the AT91RM9200, these clock inputs are connected to the Master Clock (MCK), to the Slow Clock (SLCK) and to divisions of the Master Clock. For details, see Control” ...
Page 33
... Write-though and Write-back Operation – Pseudo-random or Round-robin Replacement – Low-power CAM RAM Implementation • Write Buffer – 16-word Data Buffer – 4-address Address Buffer – Software Control Drain 1768I–ATARM–09-Jul-09 ™ (Advanced Microprocessor Bus Architecture) bus interface AT91RM9200 ™ Thumb family of high-performance 33 ...
Page 34
... Access Permission for Large Pages and Small Pages Can be Specified Separately – 16 Embedded Domains – 64-entry Instruction TLB and 64-entry Data TLB • 8-, 16-, 32-bit Data Bus for Instructions and Data AT91RM9200 34 for Each Quarter of the Pages 1768I–ATARM–09-Jul-09 ...
Page 35
... Bus Instruction Modified Virtual Address Bus Instruction Bus CP15 Data Bus Write Buffer Data Modified Virtual Data Address Physical Bus Address Bus Data MMU Data Index Bus AT91RM9200 Bus Interface Write Back Write Back PA TAG RAM Physical Address Bus Memory Controller 35 ...
Page 36
... Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer. Table 11-1. User and System Mode AT91RM9200 36 ARM9TDMI Modes and Register Layout Supervisor Undefined Mode Abort Mode Mode ...
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... Mode Abort Mode R10 R10 R11 R11 R12 R12 R13_SVC R13_ABORT R13_UNDEF R14_SVC R14_ABORT R14_UNDEF PC PC CPSR CPSR SPSR_ABO SPSR_UND SPSR_SVC RT AT91RM9200 Fast Interrupt Interrupt Mode Mode Mode R8_FIQ R9 R9 R9_FIQ R10 R10 R10_FIQ R11 R11 R11_FIQ R12 R12 R12_FIQ R13_IRQ ...
Page 38
... Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. AT91RM9200 38 1768I–ATARM–09-Jul-09 ...
Page 39
... Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the 1768I–ATARM–09-Jul-09 gives the ARM instruction mnemonic list. Mnemonic UMULL UMLAL STRH STRB STRBT STRT SWPB AT91RM9200 Operation CDP Coprocessor Data Processing MVN Move Not ADC Add with Carry SBC Subtract with Carry RSC ...
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... Branch and Exchange LDR Load Word LDRH Load Half Word LDRB Load Byte LDRSH Load Signed Halfword LDMIA Load Multiple PUSH Push Register to stack AT91RM9200 40 gives the Thumb instruction mnemonic list. Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR ...
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... TLB lockdown 11 Reserved 12 Reserved (2) 13 FCSE PID 14 Reserved 15 Test configuration 1. TLB: Translation Lookaside Buffer 2. FCSE PID: Fast Context Switch Extension Process Identifier AT91RM9200 Table 11-4. Access Read-only Read/Write Read/Write Read/Write None Read/Write Read/Write Write-only Write-only Read/Write Read/Write None None ...
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... Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • Cond [31:28]: Condition AT91RM9200 ...
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... The memory system can abort during line fetches, memory accesses and translation table access. 1768I–ATARM–09-Jul-09 Mapping Details Mapping Size Access Permission By 1M byte Section 64K bytes 4 separated subpages 4K bytes 4 separated subpages 1K byte Tiny Page AT91RM9200 Subpage Size - 16K bytes 1K byte - 50. “CP15 43 ...
Page 44
... MMU cannot cause linefill or data access via the AMBA ASB interface. Write-though Operation When a cache hit occurs for a data access, the cache line that contains the data is updated to contains its value. The new data is also immediately written to the main memory. AT91RM9200 44 “CP15 Register 1, Control” on page 48. ...
Page 45
... RAM. If this line has to be written back to the main memory, the PA TAG RAM is read and the physical address is used by the AMBA ASB interface to perform the write-back. For a 16-Kbyte DCache, the PA TAG RAM is organized by eight segments with: • 64 rows per segments • 26 bits per rows • be 1768I–ATARM–09-Jul-09 AT91RM9200 45 ...
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... Architecture Details the implementor architecture code. 0x2 value means ARMv4T architecture. • SRev[23:20]: Specification Revision Number 0x1 value; specification revision number used to distinguished two variants of the same primary part. • imp[31:24]: Implementor Code 0x41 (= A); means ARM Ltd. AT91RM9200 imp 21 ...
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... Indicates if the cache is unified or has separate instruction and data caches. Set to 1, this field indicates separate Instruction and Data caches. • ctype[28:25]: Cache Type Defines the cache type. For details on bits DSize and ISize, refer to the ARM920T Technical Reference Manual, Rev. DDI0151C. 1768I–ATARM–09-Jul- DSize ISize AT91RM9200 26 25 ctype ...
Page 48
... Modifies the MMU protection system. For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. • R[9]: ROM Protection Modifies the MMU protection system. For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. • I[12]: ICache Control 0 = ICache disabled ICache enabled. AT91RM9200 ...
Page 49
... Points to the first-level translation table base. Read returns the currently active first-level translation table. Write sets the pointer to the first-level table to the written value. The non-defined bits should be zero when written and are unpredictable when read. 1768I–ATARM–09-Jul-09 nF Clocking mode 0 Fast Bus 1 Synchronous 0 Reserved 1 Asynchronous Pointer Pointer AT91RM9200 ...
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... D15 to D0: Named Domain Access The 2-bit field value allows domain access as described in the table below. Value Access access 0 1 Client 1 0 Reserved 1 1 Manager 11.7.5 CP15 Register 4, Reserved Any access (Read or Write) to this register causes unpredictable behavior. AT91RM9200 D14 D10 Description ...
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... MVA associated with the data abort (stored in the FAR). • Domain[7:4]: Domain Indicates the domain (D15 - D0) being accessed when the fault occurred. The non-defined bits should be zero when written and are unpredictable when read. 1768I–ATARM–09-Jul- AT91RM9200 Status 51 ...
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... Invalidate ICache and DCache Clean DCache singe entry (using MVA) Clean DCache single entry (using index) Drain write buffer Prefetch ICache line (using MVA) Clean and Invalidate DCache entry (using MVA) Clean and Invalidate DCache entry (using index) AT91RM9200 FAR 21 20 ...
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... MVA format – index format Below are the details of CP15 Register 7, or Cache Function Register, in MVA format mva • mva[31:5]: Modified Virtual Address The non-defined bits should be zero when written and are unpredictable when read. 1768I–ATARM–09-Jul- mva mva mva AT91RM9200 ...
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... Line Determines the cache line. • set[7:5]: Segment Determines the cache segment. The non-defined bits should be zero when written and are unpredictable when read. Writing other opcode_2 values or CRm values is unpredictable. Reading from CP15 Register 7 is unpredictable. AT91RM9200 index 21 ...
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... The non-defined bits should be zero when written and are unpredictable when read. Writing other opcode_2 values or CRm values is unpredictable. Reading from CP15 Register 8 is unpredictable. 1768I–ATARM–09-Jul-09 MVA format MVA format mva mva mva AT91RM9200 Data CRm SBZ 5 5 SBZ 6 6 SBZ opcode_2 0 ...
Page 56
... Victim Pointer Current victim pointer that specifies the cache line to be used as victim for the next linefill. The non-defined bits should be zero when written and are unpredictable when read. AT91RM9200 56 Data Base Victim = Base Base Victim = Base 29 28 ...
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... The non-defined bits should be zero when written and are unpredictable when read. 11.7.12 CP15 Registers 11, 12, Reserved Any access (Read or Write) to these registers causes unpredictable behavior. 1768I–ATARM–09-Jul-09 TLB lockdown TLB lockdown TLB lockdown TLB lockdown Base AT91RM9200 Data CRm “CP15 Register 8, TLB Opcode_2 ...
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... CP15 Register 14, Reserved Any access (Read or Write) of these registers causes unpredictable behavior. 11.7.15 CP15 Register 15, Test Configuration Register CP15 Register 15, or Test Configuration Register, is used for test purposed. Any access (write or read) to this register causes unpredictable behavior. AT91RM9200 FCSEPID 21 20 ...
Page 59
... Debug and Test Features (DBG Test) 12.1 Overview The AT91RM9200 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions such as download- ing code and single-stepping through programs. An ETM (Embedded Trace Macrocell) provides more sophisticated debug features such as address and data comparators, half-rate clock mode, counters, sequencer and FIFO ...
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... Block Diagram Figure 12-1. AT91RM9200 Debug and Test Block Diagram AT91RM9200 60 ICE/JTAG Boundary TAP Port ARM9TDMI ICE ETM ARM920T PDC DBGU Reset and Test TMS TCK TDI NTRST JTAGSEL TDO TPK0-TPK15 TPS0-TPS2 TSYNC 2 TCLK DTXD DRXD TST0-TST1 NRST TAP: Test Access Port ...
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... The Trace Port interface is used for tracing information. A software debug- ger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. AT91RM9200-based Application Debug and Trace Environment Example 12.4 Test Environment Figure 12-3 the tester. In this example, the “ ...
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... Figure 12-3. AT91RM9200-based Application IEEE1149.1 Test Environment Example 12.5 Debug and Test Pin Description Table 12-1. Debug and Test Pin List Pin Name NRST TST0 TST1 TCK TDI TDO TMS NTRST JTAGSEL TSYNC TCLK TPS0- TPS2 TPK0 - TPK15 DRXD DTXD AT91RM9200 ...
Page 63
... For further details on the Debug Unit and the Boot program, see 12.6.4 Embedded Trace Macrocell The AT91RM9200 features an Embedded Trace Macrocell (ETM), which is closely connected to the ARM9TDMI Processor. The Embedded Trace is a standard mid-level implementation and contains the following resources: • Four pairs of address comparators • ...
Page 64
... One external output • One 18-byte FIFO The Embedded Trace Macrocell of the AT91RM9200 works in half-rate clock mode and thus integrates a clock divider. This assures that the maximum frequency of all the trace port signals do not exceed one half of the ARM920T clock speed. ...
Page 65
... A data comparator has both a value register and a mask register, therefore it is possible to com- pare only certain bits of a preprogrammed value against the data bus. 1768I–ATARM–09-Jul-09 Trace ARM920T Control Bus Tracker Trace Enable, View Data TAP Trigger, Sequencer, Counters Controller Scan Chain 6 AT91RM9200 TPS-TPS0 FIFO TPK15-TPK0 TSYNC ETM9 65 ...
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... The half-rate mode is implemented to maintain the signal clock integrity of high speed systems (up to 100 Mhz). Figure 12-5. Care must be taken on the choice of the trace capture system as it needs to support half-rate clock functionality. AT91RM9200 66 ETM Memory Map Inputs Layout Region Access type ...
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... Each AT91RM9200 input pin has a corresponding bit in the Boundary Scan Register for observability. Each AT91RM9200 output pin has a corresponding 2-bit register in the BSR. The OUTPUT bit contains data which can be forced on the pad. The CTRL bit can put the pad into high impedance. 1768I– ...
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... Each AT91RM9200 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CTRL bit selects the direction of the pad. Table 12-3. Bit ...
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... D9 395 394 D10 393 392 D11 391 390 D12 389 388 D[15:12] 387 D13 386 385 D14 384 AT91RM9200 Associated BSR Pin Type Cells INPUT I/O OUTPUT I/O CTRL INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT I/O ...
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... AT91RM9200 70 JTAG Boundary Scan Register (Continued) Pin Name D15 PC16/D16 PC17D17 PC18/D18 PC19/D19 PC20/D20 PC21/D21 PC22/D22 PC23/D23 PC24/D24 PC25/D25 PC26/D26 Associated BSR Pin Type ...
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... PC11/NCS5/CFCE1 328 327 326 PC12/NCS6/CFCE2 325 324 323 PC13/NCS7 322 321 320 PC14 319 318 317 PC15 316 AT91RM9200 Associated BSR Pin Type Cells INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL ...
Page 72
... AT91RM9200 72 JTAG Boundary Scan Register (Continued) Pin Name PC0/BCFK PC1/BFRDY/SMOE PC2/BFAVD PC3/BFBAA/SMWE PC4/BFOE PC5/BFWE PC6/NWAIT PA0/MISO/PCK3 PA1/MOSI/PCK0 PA2/SPCK/IRQ4 PA3/NPCS0/IRQ5 Associated BSR Pin Type Cells ...
Page 73
... PD4/ETXEN 262 261 260 PD5/ETXER 259 258 257 PD6/DTXD 256 255 254 PA6/NPCS3/RXD3 253 252 251 PA7/ETXCK/EREFCK/PCK2 250 AT91RM9200 Associated BSR Pin Type Cells INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL ...
Page 74
... AT91RM9200 74 JTAG Boundary Scan Register (Continued) Pin Name PA8/ETXEN/MCCDB PA9/ETX0/MCDB0 PA10/ETX1/MCDB1 PA11/ECRS/ECRSDV/MCDB2 PA12/ERX0/MCDB3 PA13/ERX1/TCLK0 PA14/ERXER/TCLK1 PA15/EMDC/TCLK2 PA16/EMDIO/IRQ6 PA17/TXD0/TIOA0 PA18/RXD0/TIOB0 Associated BSR Pin Type Cells ...
Page 75
... PA25/TWD/IRQ2 196 195 194 PA26/TWCK/IRQ1 193 192 191 PA27/MCCK/TCLK3 190 189 188 PA28/MCCDA/TCLK4 187 186 185 PA29/MCDA0/TCLK5 184 AT91RM9200 Associated BSR Pin Type Cells INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL ...
Page 76
... AT91RM9200 76 JTAG Boundary Scan Register (Continued) Pin Name PA30/DRXD/CTS2 PA31/DTXD/RTS2 PB0/TF0/RTS3 PB1/TK0/CTS3 PB2/TD0/SCK3 PB3/RD0/MCDA1 PB4/RK0/MCDA2 PB5/RF0/MCDA3 PB6/TF1/TIOA3 PB7/TK1/TIOB3 PB8/TD1/TIOA4 Associated BSR Pin Type Cells ...
Page 77
... PB15/RD2/ERX2 130 129 128 PB16/RK2/ERX3 127 126 125 PD7/PCK0/TSYNC 124 123 122 PD8/PCK1/TCLK 121 120 119 PD9/PCK2/TPS0 118 AT91RM9200 Associated BSR Pin Type Cells INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL ...
Page 78
... Table 12-3. Bit Number 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 AT91RM9200 78 JTAG Boundary Scan Register (Continued) Pin Name PD10/PCK3/TPS1 PD11/TPS2 PD12/TPK0 PB17/RF2/ERXDV PB18/RI1/ECOL PB19/DTR1/ERXCK 99 98 PB20/TXD1 PB21/RXD1 PB22/SCK1 91 90 ...
Page 79
... PB25/DSR1/EF100 PB26/RTS1 PB27/PCK0 PD16/TD1/TPK4 PD17/TD2/TPK5 PD18/NPCS1/TPK6 PD19/NPCS2/TPK7 PD20/NPCS3/TPK8 52 AT91RM9200 Associated BSR Pin Type Cells INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT ...
Page 80
... Table 12-3. Bit Number AT91RM9200 80 JTAG Boundary Scan Register (Continued) Pin Name 51 50 PD21/RTS0/TPK9 PD22/RTS1/TPK10 PD23/RTS2/TPK11 PD24/RTS3/TPK12 PD25/DTR1/TPK13 PD26/TPK14 PD27/TPK15 PB28/FIQ PB29/IRQ0 25 24 A0/NLB/NBS0 A[3:0]/NLB/NWR2/NBS0 23 /NBS2 22 A1/NWR2/NBS2 A[7: Associated BSR Pin Type Cells INPUT I/O OUTPUT CTRL INPUT I/O OUTPUT ...
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... A[11: A10 10 SDA10 9 A11 8 A12 7 A[15:12] 6 A13 5 A14 4 A15 3 A16/BA0 2 A17/BA1 1 A18 AT91RM9200 Associated BSR Pin Type Cells Output OUTPUT Output OUTPUT Output OUTPUT Output CTRL Output OUTPUT Output OUTPUT Output OUTPUT Output OUTPUT Output OUTPUT Output CTRL Output OUTPUT Output ...
Page 82
... Set to 0x0 = JTAGSEL is low. Set to 0x1 = JTAGSEL is high. • PART NUMBER[27:14]: Product Part Number Set to 0x5b02. • MANUFACTURER IDENTITY[11:1] Set to 0x01f. • Bit [0]: Required by IEEE Std. 1149.1 Set to 1. The AT91RM9200 ID Code value is 0x15b0203f (JTAGSEL is High). The AT91RM9200 ID Code value is 0x05b0203f (JTAGSEL is Low). AT91RM9200 ...
Page 83
... Boot Program 13.1 Overview The Boot Program is capable of downloading an application in an AT91RM9200-based system. It integrates a Bootloader and a boot Uploader to assure correct information download. The Bootloader is activated first. It looks for a sequence of eight valid ARM exception vectors in a DataFlash connected to the SPI, an EEPROM connected to the Two-wire Interface (TWI 8-bit memory device connected to the external bus interface (EBI) ...
Page 84
... Figure 13-1. Boot Program Algorithm Flow Diagram Device Setup SPI DataFlash Boot Timeout 10 ms TWI EEPROM Boot Timeout 40 ms Parallel Boot OR *DFU = Device Firmware Upgrade AT91RM9200 84 Figure 13-1. Yes Download from DataFlash Download from Yes EEPROM Yes Download from 8-bit Device ...
Page 85
... ROM 0x0000_0000 ea00000b B 0x2c00ea00000bB0x2c e59ff014 LDR PC,[PC,20]04e59ff014LDRPC,[PC,20] e59ff014 LDR PC,[PC,20]08e59ff014LDRPC,[PC,20] e59ff014 LDR PC,[PC,20]0ce59ff014LDRPC,[PC,20] e59ff014 LDR PC,[PC,20]10e59ff014LDRPC,[PC,20] 00001234 LDR PC,[PC,20]1400001234LDRPC,[PC,20] e51fff20 LDR PC,[PC,-0xf20]18e51fff20LDRPC,[PC,-0xf20] e51fff20 LDR PC,[PC,-0xf20]1ce51fff20LDRPC,[PC,-0xf20] AT91RM9200 Internal ROM 0x0010_0000 Internal SRAM 0x0000_0000 85 ...
Page 86
... An example of valid vectors: 00 004 download mode (DataFlash, EEPROM or 8-bit memory in device with EBI integrated), the size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct vector for his application. AT91RM9200 ...
Page 87
... Number of Reserved pages (Nb of pages) DataFlash Device Density 1 Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits 128 Mbits AT91RM9200 512 bytes blocks to download Page Size (bytes) Number of pages 264 512 264 1024 264 2048 264 4096 528 4096 ...
Page 88
... DataFlash connected to the NPCS0 of the SPI, followed by the serial EEPROM con- nected to the TWI and by an 8-bit parallel memory connected on NCS0 of the External Bus Interface. AT91RM9200 88 register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. ...
Page 89
... Branch instruction ? Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91RM9200 Table 13-1 summarizes the parame- No Serial DataFlash Download No 89 ...
Page 90
... Generally, serial EEPROMs have no identification code. The bootloader checks for an acknowl- edgment on the first read. The device address on the two-wire bus must be 0x0. The bootloader supports the devices listed in Table 13-3. Figure 13-7. Serial Two-Wire EEPROM Download AT91RM9200 90 Table 13-3. Supported EEPROM Devices ...
Page 91
... LDR or Branch instruction ? Yes Read the external memory into the internal SRAM (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91RM9200 No Memory uploader 91 ...
Page 92
... CRC16 Figure 13-9 AT91RM9200 92 start to 01) shows a transmission using this protocol. 1768I–ATARM–09-Jul-09 ...
Page 93
... Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Host Device Prepare for an upgrade USB reset DFU mode activated Download this firmware Prepare to exit DFU mode USB reset AT91RM9200 93 ...
Page 94
... Pin Used (1) MOSI (1) SPCK NPCS0 (1) TWD (1) TWCK Note: AT91RM9200 94 contains a list of pins that are driven during the Boot Program execution. These pins Pins Driven during Boot Program Execution SPI (DataFlash) (1) 1. See Section 10.3 “Peripheral Multiplexing on PIO Lines” on page TWI (EEPROM ...
Page 95
... Thus, using service, the client application carries out a synchronous read by starting the read and polling the status asynchronous read specifying a callback when starting the read operation. 1768I–ATARM–09-Jul-09 AT91RM9200 95 ...
Page 96
... It is possible to overload just one method of a service or all the methods of a service. In this latter case, the functionality of the service is user-defined, but still works on the same data structure. AT91RM9200 96 99). Thus, only the functions AT91F_Open_<service> are visible from 14.3.2 “ ...
Page 97
... Overloading AT91F_ChildMethod by My_ChildMethod // My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod () { } // Overloading Open Service Method AT91PS_Service My_OpenService( AT91PS_Service pService Overloading ChildMethod default value } // Allocation of the service structure AT91S_Service service; // Opening of the service AT91PS_Service pService = My_OpenService(&service); AT91RM9200 AT91F_OpenService(pService); pService->ChildMethod= My_ChildMethod; return pService; 97 ...
Page 98
... Init the service with default methods AT91PS_Service AT91F_OpenService( AT91PS_Service pService) { pService->data = 0; pService->MainMethod =AT91F_MainMethod; pService->ChildMethod=AT91F_ChildMethod; return pService; } AT91RM9200 98 Overloading AT91F_ChildMethod by My_ChildMethod // My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod () { } // Allocation of the service structure AT91S_Service service; // Opening of the service AT91PS_Service pService = AT91F_OpenService(& ...
Page 99
... AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtlTempo, void const *pTempoTimer ) { ... } AT91S_TempoStatus AT91F_CtlTempoCreate ( AT91PS_CtlTempo pCtrl, AT91PS_SvcTempo pTempo) { ... } structure. To obtain the Open Service Method of another service stored in can be found at the beginning of the ROM, after the excep- AT91S_RomBoot AT91RM9200 96). function), they must AT91F_Open_<Service> . Some members of AT91S_RomBoot structure. AT91S_RomBoot 99 ...
Page 100
... AT91S_TempoStatus AT91F_STStart(void * pTimer) // Typical Use: AT91S_CtlTempo ctlTempo; ctlTempo.CtlTempoIsStart(...); // Default Method: AT91S_TempoStatus AT91F_STIsStart( AT91PS_CtlTempo pCtrl) AT91RM9200 100 Description Member of AT91S_RomBoot structure. Corresponds to the Open Service Method for the Tempo Service. Input Parameters: Pointer on a Control Tempo Object. Pointer on a System Timer Descriptor Structure. ...
Page 101
... Number of times to reload the tempo after timeout completed for periodic execution. Callback on a method to launch once the timeout completed. Allows to have a hook on the current service. Output Parameters: Returns 1. Member of structure. AT91S_SvcTempo Force to stop a software timer. Input Parameters: Pointer on a Service Tempo Object. Output Parameters: Returns 1. AT91RM9200 ’s list. 101 ...
Page 102
... AT91S_SvcTempo svcTempo2; • Initializes the AT91S_SvcTempo object calling the AT91F_CtlTempoCreate method of the AT91S_CtlTempo service: // Init the svcTempo2, link it to the AT91S_CtlTempo object ctlTempo.CtlTempoCreate(&ctlTempo, &svcTempo2); AT91RM9200 102 ) method replaced by the application &ctlTempo, &svcTempo1 method of the svcTempo1 object. Depending on the function Start ...
Page 103
... AT91S_PipeStatus (*Reset) (struct _AT91S_Pipe *pPipe); 1768I–ATARM–09-Jul-09 pBuffer; (AT91S_PipeStatus, void *); struct _AT91S_Pipe *pPipe, char const * pData, unsigned int size, void (*callback) (AT91S_PipeStatus, void *), void *privateData); struct _AT91S_Pipe *pPipe, char *pData, unsigned int size, void (*callback) (AT91S_PipeStatus, void *), void *privateData); AT91RM9200 AT91PS_SvcComm AT91PS_Buffer *pPipe); 103 ...
Page 104
... AT91S_Buffer, *AT91PS_Buffer; Description of the The SvcComm structure provides the interface between low-level functions and the pipe object. SvcComm Structure It contains pointers of functions initialized to the lower level functions (e.g. SvcXmodem). AT91RM9200 104 (struct _AT91S_Buffer *pSBuffer, (struct _AT91S_Buffer *pSBuffer, (struct _AT91S_Buffer *pSBuffer); (struct _AT91S_Buffer *pSBuffer); ...
Page 105
... AT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int); AT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int); AT91S_SvcCommStatus (*StopTx) // Private Methods: AT91S_SvcCommStatus (*ReadHandler) int csr); 1768I–ATARM–09-Jul-09 (struct _AT91S_Service *pService); (*TxReady)(struct _AT91S_Service *pService); (*RxReady)(struct _AT91S_Service *pService); (struct _AT91PS_SvcXmodem *, unsigned int); (struct _AT91PS_SvcXmodem *, unsigned AT91RM9200 105 ...
Page 106
... AT91S_SvcComm AT91PS_USART pUsart; AT91S_SvcTempo tempo; // Link to a AT91S_Tempo object char unsigned int char unsigned char packetId; char char char } AT91S_SvcXmodem, *AT91PS_SvcXmodem AT91RM9200 106 (*GetCrc) (char *ptr, unsigned int count); (*CheckHeader) (unsigned char currentPacket, char (*CheckData) (struct _AT91PS_SvcXmodem *); parent; // Base class *pData; ...
Page 107
... Input Parameters: Pointer on a Xmodem Service Structure. csr: usart channel status register. Output Parameters: Status for xmodem read or write. sXmBuffer; // Xmodem Buffer allocation xmodemPipe;// xmodem pipe communication struct ctlTempo; // Tempo struct = pAT91->OpenSBuffer(&sXmBuffer); AT91RM9200 structure. 107 ...
Page 108
... DataFlash and DataFlash Cards for reading, programming and erasing operations. This service is based on SPI interrupts that are managed by a specific handler. It also uses the corresponding PDC registers. For more information on the commands available in the DataFlash Service, refer to the relevant DataFlash documentation. AT91RM9200 108 (AT91PS_USART) AT91C_BASE_DBGU, MCK, // Master Clock ...
Page 109
... Pointer on a DataFlash Descriptor Structure (member of the service structure). Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Member of structure AT91S_SvcDataFlash Allows to reset PDC & Interrupts. Input Parameters: Pointer on a DataFlash Descriptor Structure (member of the service structure). Output Parameters: None. AT91RM9200 109 ...
Page 110
... AT91S_SvcDataFlash svcDataFlash; svcDataFlash.ReadBuffer(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_DataFlashReadBuffer ( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int bufferAddress, unsigned char *dataBuffer, int sizeToRead ) AT91RM9200 110 Description Member of structure AT91S_SvcDataFlash Read a Page in DataFlash. Input Parameters: Pointer on DataFlash Service Structure. DataFlash address. Data buffer destination pointer. ...
Page 111
... Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer command. Pointer on data buffer to write. Address in the internal buffer. Number of bytes to write. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Returns 4 if DataFlash Bad Command. Returns 5 if DataFlash Bad Address. AT91RM9200 111 ...
Page 112
... Default Method: AT91S_SvcDataFlashStatus AT91F_MainMemoryToBufferCompare( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int page) Note: AT91S_SvcDataFlashStatus corresponds to an unsigned int. AT91RM9200 112 Description Member of structure. AT91S_SvcDataFlash Write Internal Buffer to the DataFlash Main Memory. Input Parameters: Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer command. ...
Page 113
... Now the different methods can be used. Following is an example of a Page Read of 528 bytes on page 50: // Result of the read operation in RxBufferDataFlash unsigned char RxBufferDataFlash[528]; svcDataFlash.PageRead(&svcDataFlash, 1768I–ATARM–09-Jul-09 AT91S_SvcDataFlash instance by calling the AT91S_SvcDataFlash : SPI Interrupt AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE service structure: AT91S_SvcDataFlash (50*528),RxBufferDataFlash,528); AT91RM9200 AT91F_OpenSvcDataFlash and in the application AT91S_Dataflash AT91F_OpenSvcDataFlash using 113 ...
Page 114
... Typical Use: pAT91->CRCCCITT(...); // Default Method: void CalculateCrc16ccitt( const unsigned char *address, unsigned int size, unsigned short *crc) AT91RM9200 114 AT91S_RomBoot Description This function provides a table driven 32bit CRC generation for byte data. This CRC is known as the CCITT CRC32. Input Parameters: Pointer on the data buffer ...
Page 115
... Step of the sine. Corresponds to the precision of the amplitude calculation. Depends on the Sine Array used. Here, the array has 256 values (thus 256 steps) of amplitude for 180 degrees. Output Parameters: Amplitude of the sine waveform. Sine Array with a resolution of 256 values for 180 degrees. AT91RM9200 structure. 115 ...
Page 116
... AT91RM9200 116 1768I–ATARM–09-Jul-09 ...
Page 117
... AT91RM9200 Reset Controller 15.1 Overview This chapter describes the AT91RM9200 reset signals and how to use them in order to assure correct operation of the device. The AT91RM9200 has two reset input lines called NRST and NTRST. Each line provides, respectively: • Initialization of the User Interface registers (defined in the user interface of each peripheral) and: – ...
Page 118
... NRST pin. In fact, the cold reset assertion has to overlap the start-up time of the system. The user reset request requires a shorter assertion delay time than does cold reset. 15.1.2.2 Test Access Port (TAP) Reset Test Access Port (TAP) reset functionality is provided through the NTRST signal. AT91RM9200 118 1. VDD is applicable to VDD , VDD IOM ...
Page 119
... Figure 15-3 together during production as shown in example (2) of 15.1.3 Required Features for the Reset Controller The following table presents the features required of a reset controller in order to obtain an opti- mal system with the AT91RM9200 processor. Table 15-2. Reset Controller Functions Synthesis Feature Description Power Supply Monitoring Overlaps the transient state of the system during power-up/down and brownout ...
Page 120
... AT91RM9200 120 1768I–ATARM–09-Jul-09 ...
Page 121
... Chip Select 0 of the EBI. The Remap command switches addressing of the ARM vectors (0x0 - 0x20) on the embedded SRAM. Key Features of the AT91RM9200 Memory Controller are: • Programmable Bus Arbiter Handling Four Masters – Internal Bus is Shared by ARM920T, PDC, USB Host Port and Ethernet MAC – ...
Page 122
... Block Diagram Figure 16-1. Memory Controller Block Diagram ARM920T Processor Abort EMAC DMA UHP DMA Peripheral Data Controller AT91RM9200 122 Memory Controller Abort Status Address Decoder Bus Misalignment Detector Arbiter User Interface APB Bridge Peripheral 0 APB Peripheral 1 Peripheral N ASB Internal ...
Page 123
... Eight 256-Mbyte address spaces, each assigned to one of the eight chip select lines of the External Bus Interface • One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 1536M bytes that returns an Abort if accessed 1768I–ATARM–09-Jul-09 AT91RM9200 123 ...
Page 124
... When the address of the access is undefined within the internal memory area, i.e. over the address 0x0040 0000, the Address Decoder returns an Abort to the master. AT91RM9200 124 shows the assignment of the 256-Mbyte memory areas. ...
Page 125
... Internal Memory Area 3 USB Host Port 0x003F FFFF 0x0040 0000 Undefined Area 0x0FFF FFFF Internal Memory Area Depending on BMS and the Remap Command 1 Internal ROM AT91RM9200 1M Byte 1M Byte 1M Byte 1M Byte 252M bytes (Abort) Before Remap After Remap 0 External Memory Area 0 ...
Page 126
... So, in this case preferable to use the content of the Abort Link register of the ARM processor. AT91RM9200 126 is provided to summarize the effect of these two key features on the Figure 16-1) ...
Page 127
... Memory Controller, which can neither enable/disable it nor return its activity. This Memory Controller interrupt signal is ORed with the other System Peripheral interrupt lines (RTC, ST, DBGU, PMC) to provide the System Interrupt on Source 1 of the Advanced Interrupt Controller. 1768I–ATARM–09-Jul-09 AT91RM9200 Figure 127 ...
Page 128
... User Interface Base Address: 0xFFFFFF00 AT91RM9200 Memory Controller Memory Map Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x0C MC Master Priority Register 0x10 - 0x5C Reserved 0x60 EBI Configuration Registers AT91RM9200 128 Name Access ...
Page 129
... This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 1768I–ATARM–09-Jul- – – – – – – – – – – – – AT91RM9200 – – – – – – – – – – – RCB 129 ...
Page 130
... ABTSZ: Abort Size Status ABTSZ • ABTTYP: Abort Type Status ABTTYP • MST0: ARM920T Abort Source 0: The last aborted access was not due to the ARM920T. 1: The last aborted access was due to the ARM920T. AT91RM9200 130 – – SVMST3 – – MST3 – – – ...
Page 131
... At least one abort due to the UHP occurred since the last read of MC_ASR. • SVMST3: Saved EMAC Abort Source 0: No abort due to the EMAC occurred since the last read of MC_ASR notified in the bit MST3 least one abort due to the EMAC occurred since the last read of MC_ASR. 1768I–ATARM–09-Jul-09 AT91RM9200 131 ...
Page 132
... MSTP0: ARM920T Priority • MSTP1: PDC Priority • MSTP2: UHP Priority • MSTP3: EMAC Priority 000: Lowest priority 111: Highest priority In the case of equal priorities, Master 0 has highest and Master 3 has lowest priority. AT91RM9200 132 ABTADD ABTADD 13 12 ...
Page 133
... SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support – Static Memory Controller on NCS4 - NCS6, Optional NAND Flash/SmartMedia and – Static Memory Controller on NCS7 Note: 1768I–ATARM–09-Jul-09 (1) CompactFlash Support 1. The 32-bit Data Bus is for SDRAM only. AT91RM9200 133 ...
Page 134
... Block Diagram Figure 17-1 Figure 17-1. Organization of the External Bus Interface Memory Controller ASB Address Decoder AT91RM9200 134 below shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Burst Flash Logic Controller Static Memory Controller NAND Flash/ ...
Page 135
... NWR[3:0] Write Signals NBS[3:0] Byte Mask Signals SDA10 SDRAM Address 10 Line 1768I–ATARM–09-Jul-09 EBI SMC EBI for CompactFlash Support EBI for NAND Flash/SmartMedia Support SDRAM Controller AT91RM9200 Type Active Level I/O Output Output Low Output Low Output Low Output Low ...
Page 136
... A10 A12 Not Supported A[14:13] A[12:11] A[25:15] Not Supported D[31:16] D[31:16] D[15:0] D[15:0] AT91RM9200 136 Burst Flash Controller below details the connections between the three Memory Controllers and the EBI BFC I/O Lines Not Supported Not Supported A0 A[10:1] Not Supported A11 ...
Page 137
... A22 - A23 A24 A24 A24 – – – – – – – ( – AT91RM9200 NAND Flash/ SDRAM CompactFlash SmartMedia SDRAMC SMC AD0 - AD7 D8 - D15 D16 - D31 – DQM0 A0 DQM2 A10 A9 – A10 – – – A11 - A12 – – – BA0 – ...
Page 138
... The REG signal of the CompactFlash can be driven by any of the following address bits: A24, A22 to A11. For details, see Section 17.6.6 “CompactFlash Support” on page 4. NWR1 enables upper byte writes. NWR0 enables lower byte writes. AT91RM9200 138 Pins of the Interfaced Device 2 x 8-bit ...
Page 139
... NBS2 Burst Flash D0-D15 D0-D15 A1-A21 A0-A20 CE CLK OE WE AVD RDY 128K x 8 SRAM A1-A17 D0-D7 A0-A16 D0- NRD/NOE WE A0/NWR0/NBS0 AT91RM9200 SDRAM D8-D15 D0-D7 CS CLK A0-A9, A11 A2-A11, A13 CKE SDWE A10 SDA10 WE BA0 A16/BA0 RAS BA1 A17/BA1 CAS DQM NBS1 SDRAM ...
Page 140
... Static Memory Controller For information on the Static Memory Controller, refer to the SMC page 155. 17.6.4 SDRAM Controller For information on the SDRAM Controller, refer to the SDRAMC description on “Overview” on page AT91RM9200 140 193. Section 18.1 “Description” on Section 19.1 1768I–ATARM–09-Jul-09 ...
Page 141
... In the above example, the A22 pin of the EBI can be used to drive the REG signal of the Compact- Flash Device. Section 18.6.5 “Setup and Hold Cycles” on page 168 AT91RM9200 Section 20.1 “Overview” on page to the appropriate value enables this logic. A23 = 1 ...
Page 142
... EBI signals on the EBI pins. The EBI pins in cated to the CompactFlash interface as soon as the CS4A field of the Chip Select Assignment Register is set pins must not be used to drive any other memory devices. AT91RM9200 142 External Bus Interface SMC ...
Page 143
... CompactFlash Signals CFCS CFCE1 CFCE2 Access to CompactFlash Device CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW below illustrates an example of a CompactFlash application. CFCS and CFRNW AT91RM9200 CS4A = 0 EBI Signals NCS4 NCS5 NCS6 Access to Other EBI Devices EBI Signals NRD/NOE NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25 Section 18.1 “ ...
Page 144
... The SMWE and SMOE signals are multiplexed with BFRDY and BFBAA signals of the Burst Flash Controller. This multiplexing is controlled in the MUX logic part of the EBI by the CS3A field of the Chip Select Assignment Register Register” on page 152.) AT91RM9200 144 EBI D[15:0] ...
Page 145
... Flash device will occur when the NAND Flash/SmartMedia device is activated due to the fact that the SMOE and SMWE signals are mul- tiplexed with BFRDY and BFBAA signals respectively. 1768I–ATARM–09-Jul-09 MUX Logic NAND Flash/Smart Media Logic SMOE SMWE AT91RM9200 BFRDY_SMOE BFBAA_SMWE CS3A 145 ...
Page 146
... Figure 17-7. NAND Flash/SmartMedia Application Example AT91RM9200 146 D[7:0] A[22:21] NCS3/SMCS Not Connected EBI BFBAA/SMWE BFRDY/SMOE PIO PIO AD[7:0] ALE CLE NAND Flash/SmartMedia NWE NOE CE R/B 1768I–ATARM–09-Jul-09 ...
Page 147
... Select Assignment Register located in the bus matrix memory space • Initialize the SDRAM Controller accordingly to SDRAM device and system bus frequency. The Data Bus Width programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM Device Initialization” part of the SDRAM controller. 1768I–ATARM–09-Jul-09 AT91RM9200 147 ...
Page 148
... The Data Bus Width programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the “SDRAM Device Initialization” part of the SDRAM controller. AT91RM9200 148 1768I–ATARM–09-Jul-09 ...
Page 149
... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on a 16-bit non-volatile memory at slow clock. For other configurations, configure Static Memory Controller CS0 Setup, Pulse, Cycle and Mode accordingly to Flash timings and system bus frequency. 1768I–ATARM–09-Jul-09 AT91RM9200 149 ...
Page 150
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91RM9200 150 1768I–ATARM–09-Jul-09 ...
Page 151
... External Bus Interface (EBI) User Interface AT91RM9200 EBI User Interface Base Address: 0xFFFF FF60 Table 17-7. External Bus Interface Memory Map Offset Register 0x00 Chip Select Assignment Register 0x04 Configuration Register 0x08 Reserved 0x0C Reserved 0x10 - 0x2C SMC User Interface ...
Page 152
... Chip Select 4 is assigned to the Static Memory Controller and NCS4, NCS5 and NCS6 behave as defined by the SMC Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. Accessing the address space reserved to NCS5 and NCS6 may lead to an unpredictable outcome. AT91RM9200 152 29 ...
Page 153
... Data Bus bits are internally pulled-up to the VDDIOM power supply [D15:0] Data Bus bits are not internally pulled-up. 1768I–ATARM–09-Jul- – – – – – – – – – – – – AT91RM9200 – – – – – – – – – – DBPUC 153 ...
Page 154
... AT91RM9200 154 1768I–ATARM–09-Jul-09 ...
Page 155
... It also provides an external wait request capability. 18.2 Block Diagram Figure 18-1. Static Memory Controller Block Diagram SMC Memory Chip Select Controller MCK PMC 1768I–ATARM–09-Jul-09 SMC User Interface APB AT91RM9200 PIO Controller NCS[7:0] NRD NWR0/NWE NWR1/NUB A0/NLB A[22:1] D[15:0] NWAIT 155 ...
Page 156
... Output Output Output Output Output Output 18.6.1.3 “Data Bus Width” on page 158. 18.6.2.1 “Write Access Type” on page 18.6.2.1 “Write Access Type” on page AT91RM9200 Type Active Level Low Low Low Low Low I/O Input Low 159. ...
Page 157
... The Static Memory Controller provides up to eight chip select lines: NCS0 to NCS7. 1768I–ATARM–09-Jul- Byte Device Low Hi 1M Byte Device Low Hi 1M Byte Device Low Hi 1M Byte Device Low AT91RM9200 Figure 18-2. Base + 4M Bytes Repeat 3 Base + 3M Bytes Repeat 2 Base + 2M Bytes Repeat 1 Base + 1M Byte Base 157 ...
Page 158
... A data bus width bits can be selected for each chip select. This option is controlled by the DBW field in the SMC_CSR for the corresponding chip select. See ters” on page Figure 18-4 Figure 18-4. Memory Connection for an 8-bit Data Path Device Figure 18-5 AT91RM9200 158 (1) NCS1 NCS0 190 ...
Page 159
... Figure 18-6 1768I–ATARM–09-Jul-09 D[7:0] D[15:8] A[22:1] NLB SMC NUB NWE NRD NCS2 shows how to connect two 512K x 8-bit devices in parallel on NCS2 (BAT = 0) AT91RM9200 D[7:0] D[15:8] A[22:0] Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable 190. 159 ...
Page 160
... The signal NWR0/NWE is used as NWE and enables writing for byte or half-word. • The signal NRD enables reading for byte or half-word. Figure 18-7 device type) on NCS2 (BAT = 1). Figure 18-7. Connection to a 16-bit Data Path Device with Byte and Half-word Access Figure 18-8 on NCS2 (BAT = 1). AT91RM9200 160 D[7:0] D[15:8] A[22:1] A0 SMC ...
Page 161
... D[15:0] Figure 18-10. Write Access with 1 Wait State 1768I–ATARM–09-Jul-09 D[7:0] D[15:8] A[19:1] NLB SMC NUB NWE NRD NCS2 Figure 18-9 MCK A[22:0] NCS NWE D[15:0] AT91RM9200 D[7:0] D[15:8] A[18:0] Write Enable Output Enable Memory Enable and Figure 18-10. 161 ...
Page 162
... NRD remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol can allow a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contentions on the external bus. AT91RM9200 162 In the following waveforms and descriptions NWE represents NWE, NWR0 and NWR1 unless NWR0 and NWR1 are otherwise represented. In addition, NCS represents NCS[7:0] (see “ ...
Page 163
... NWE pulse is held low: 0 wait states 1 wait state For each additional wait state programmed, an additional cycle is added. 1768I–ATARM–09-Jul-09 MCK A[22:0] NCS NRD D[15:0] (“SMC Chip Select Registers” on page AT91RM9200 190). The number of cycles to insert is pro- 1/2 clock cycle 1 clock cycle 163 ...
Page 164
... NWS must be programmed as a function of synchronization time and delay between NWAIT fall- ing and control signals falling (NRD/NWE), otherwise SMC will not function correctly. NWS Note: WARNING: If NWAIT is asserted during a setup or hold timing, the SMC does not function correctly. AT91RM9200 164 1 Wait State Access MCK NCS NWE ...
Page 165
... The Data Float Output Time (t field of the SMC_CSR register for the corresponding chip select 1768I–ATARM–09-Jul-09 (2) NWAIT Synchronization Delay NWAIT Synchronization Delay ) for each external memory device is programmed in the TDF DF AT91RM9200 (“SMC Chip Select Registers” 165 ...
Page 166
... If a wait state has already been inserted (e.g., data float wait state), then no more wait states are added. AT91RM9200 166 190). The value of TDF indicates the number of data float wait cycles (between 0 and ...
Page 167
... NWE D[15:0] 1768I–ATARM–09-Jul-09 Mem 1 Chip Select Wait addr Mem 1 addr Mem 2 (1) (2) 1. Early Read Protocol 2. Standard Read Protocol Figure 18-18). This wait state is generated in addition to any other pro- Write Cycle Early Read Wait AT91RM9200 Mem 2 Read Cycle 167 ...
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... MCK A[22:0] NRD NRD Setup Figure 18-20. Read Access with Setup MCK A[22:0] NRD AT91RM9200 168 170 programmed on the first memory bank and when the second DF is higher or equal to the number of setup cycles, the number of setup DF Figure 18-24 on page Figure 18-25 on page 171) ...
Page 169
... Figure 18-21. Write Access with Setup and Hold MCK A[22:0] NWE D[15:0] NWR Setup Figure 18-22. Write Access with Setup MCK A[22:0] NWE D[15:0] 1768I–ATARM–09-Jul-09 Pulse Length NWR Setup Pulse Length AT91RM9200 NWR Hold NWR Hold 169 ...
Page 170
... Figure 18-23. Consecutive Accesses with Setup Programmed on the Second Access MCK A[22:0] NCS1 NCS2 NWE NRD Figure 18-24. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 1) MCK A[22:0] NCS1 NCS2 NRD D[15:0] AT91RM9200 170 Setup Setup Data Float Time 1768I–ATARM–09-Jul-09 ...
Page 171
... Additionally, WSEN must be set and NWS programmed with a value of two or more superior to ACSS. In LCD mode not recommended to use RWHOLD or RWSETUP. If the above condi- tions are not satisfied, SMC does not operate correctly. 1768I–ATARM–09-Jul-09 Setup Data Float Time 190). AT91RM9200 (“SMC Chip 171 ...
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... ACCS D[15:0] 18.6.7 Memory Access Waveforms 18.6.7.1 Read Accesses in Standard and Early Protocols Figure 18-28 on page 173 for external memory read protocol. AT91RM9200 172 ACSS = 3, NWEN = 1, NWS = 10 ACCS = 2, NWEN = 1, NWS = 10 through Figure 18-31 on page 176 ACSS ACCS show examples of the alternatives ...
Page 173
... Figure 18-28. Standard Read Protocol without t Read Mem 1 MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) 1768I–ATARM–09-Jul-09 DF Write Mem 1 Read Mem 1 Read Mem 2 Chip Select Change Wait t WHDX AT91RM9200 Write Mem 2 Read Mem 2 t WHDX 173 ...
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... Figure 18-29. Early Read Protocol without t Read Mem 1 MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) AT91RM9200 174 DF Write Early Read Read Mem 1 Wait Cycle Mem 1 Mem 2 Chip Select Change Wait t WHDX Read Write Early Read Mem 2 ...
Page 175
... Mem 1 Read Mem 1 Data Float Wait MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) 1768I–ATARM–09-Jul-09 DF Write Read Mem 2 Read Mem 1 Data Float Wait WHDX AT91RM9200 Write Write Mem 2 Mem 2 Read Mem 2 Data Float Wait 175 ...
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... NCS1 NCS2 t DF D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) 18.6.7.2 Accesses with Setup and Hold Figure 18-32 Hold Cycles. AT91RM9200 176 DF Early Read Read Wait Mem 2 Read Mem 1 Data Float Wait t DF and Figure 18-33 show an example of read and write accesses with Setup and ...
Page 177
... A[22:1] 008cb A0/NLB NRD NWR0/NWE NWR1/NUB NCS 3000 D[15:0] e3a0 Setup Note: 1. Write access, memory data bus width = 8, RWSETUP = 1, RWHOLD = 1, WSEN = 1, NWS = 0 1768I–ATARM–09-Jul-09 (1) 00028 Hold Setup 0001 (1) 00082 0605 Setup Hold AT91RM9200 00d2c Hold 0002 008cc 0606 Hold 177 ...
Page 178
... NWAIT internally synchronized A[22:1] 000008A NRD NWR0/NWE A0/NLB NWR1/NUB NCS D[15:0] 1312 Wait Delay Falling from NWR0/NWE Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 6 AT91RM9200 178 through Figure 18-37 on page 181 (1) show examples of accesses using 1768I–ATARM–09-Jul-09 ...
Page 179
... Figure 18-35. Write Access using NWAIT in Byte Write Type Access Chip Select Wait MCK NWAIT NWAIT internally synchronized 000008C A[22:1] A0/NLB NRD NWR0/NWE NWR1/NUB NCS D[15:0] Wait Delay Falling from NWR0/NWE/NWR1/NUB Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 5 1768I–ATARM–09-Jul-09 (1) 1716 AT91RM9200 179 ...
Page 180
... Figure 18-36. Write Access using NWAIT Chip Select Wait MCK NWAIT NWAIT internally synchronized 0000033 A[22:1] A0/NLB NRD NWR0/NWE NWR1/NUB NCS D[15:0] Wait Delay Falling from NWR0/NWE Note: 1. Write access memory, data bus width = 8 bits, WSEN = 1, NWS = 4 AT91RM9200 180 (1) 0403 1768I–ATARM–09-Jul-09 ...
Page 181
... Figure 18-43 Figure 18-44 1768I–ATARM–09-Jul-09 (1) 0003 through Figure 18-44 on page 188 Table 18-3. Memory Access Waveforms Number of Wait States AT91RM9200 show the waveforms for read and Bus Width Size of Data Transfer 16 Word 16 Word 16 Half-word 8 Word 8 Half-word 8 Byte 16 Byte 181 ...
Page 182
... Figure 18-38. 0 Wait State, 16-bit Bus Width, Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] AT91RM9200 182 addr+1 addr ...
Page 183
... Figure 18-39. 1 Wait State, 16-bit Bus Width, Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] 1768I–ATARM–09-Jul-09 1 Wait State addr AT91RM9200 1 Wait State addr 183 ...
Page 184
... Figure 18-40. 1 Wait State, 16-bit Bus Width, Half-Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] AT91RM9200 184 1 Wait State 1768I–ATARM–09-Jul-09 ...
Page 185
... Figure 18-41. 0 Wait State, 8-bit Bus Width, Word Transfer MCK addr A[22:0] NCS Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] 1768I–ATARM–09-Jul-09 addr+1 addr AT91RM9200 addr 185 ...
Page 186
... Figure 18-42. 1 Wait State, 8-bit Bus Width, Half-Word Transfer 1 Wait State MCK A[22:0] NCS Read Access · Standard Read, Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] AT91RM9200 186 1 Wait State Addr Addr 1768I–ATARM–09-Jul-09 ...
Page 187
... Figure 18-43. 1 Wait State, 8-bit Bus Width, Byte Transfer MCK A[22:0] NCS Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] 1768I–ATARM–09-Jul-09 1 Wait State AT91RM9200 XB 1 187 ...
Page 188
... A[22:1] Internal Address Bus NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write Option NWR0 NWR1 D[15:0] · Byte Select Option NWE AT91RM9200 188 addr addr addr addr 1768I– ...
Page 189
... SMC Chip Select Register 3 0x10 SMC Chip Select Register 4 0x14 SMC Chip Select Register 5 0x18 SMC Chip Select Register 6 0x1C SMC Chip Select Register 7 1768I–ATARM–09-Jul-09 AT91RM9200 Table 18-4. Eight Chip Select Registers Name Access SMC_CSR0 Read-write SMC_CSR1 Read-write SMC_CSR2 ...
Page 190
... BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus. 0: Chip select line is connected to two 8-bit wide devices. 1: Chip select line is connected to a 16-bit wide device. AT91RM9200 190 – ...
Page 191
... Three cycles less at the beginning and the end of the access. . NWR Setup (2) or ½ cycle 0 ( ½ cycles ½ cycles ½ cycles ½ cycles ½ cycles ½ cycles ½ cycles 1 “Setup and Hold Cycles” on page 168 192. AT91RM9200 (1) (4) (5) RWHOLD NRD Hold cycles cycles cycles cycles cycles 1 0 ...
Page 192
... Figure 18-45. Read-write Setup Figure 18-46. Read Hold A[22:0] Figure 18-47. Write Hold A[22:0] D[15:0] AT91RM9200 192 MCK A[22:0] NRD NWE RWSETUP MCK NRD RWHOLD MCK NWE RWHOLD 1768I–ATARM–09-Jul-09 ...
Page 193
... Energy-saving Capabilities – Self-refresh and Low-power Modes Supported • Error Detection – Refresh Error Interrupt • SDRAM Power-up Initialization by Software • Latency is Set to Two Clocks (CAS Latency Not Supported) • Auto Precharge Command Not Used 1768I–ATARM–09-Jul-09 AT91RM9200 193 ...
Page 194
... BA[1:0] Bank Select Signals RAS Row Signal CAS Column Signal SDWE SDRAM Write Enable NBS[3:0] Data Mask Enable Signals A[12:0] Address Bus D[31:0] Data Bus AT91RM9200 194 SDRAMC SDRAMC Chip Select SDRAMC Interrupt MCK PMC User Interface APB PIO Controller SDCK ...
Page 195
... SDRAM device memory mapping therefore seen CPU Address Line Row[10:0] Row[10:0] Row[10:0] Row[10:0] CPU Address Line Row[11:0] Row[11:0] Row[11:0] Row[11:0] CPU Address Line Row[12:0] Row[12:0] Row[12:0] AT91RM9200 Column[7:0] Column[8:0] Column[9:0] Column[10: Column[7:0] Column[8:0] Column[9:0] Column[10: Column[7:0] Column[8:0] Column[9:0] Column[10: ...
Page 196
... Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Table 19-7. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Notes the byte address inside a 16-bit half-word. 2. Bk[1] = BA1, Bk[0] = BA0. AT91RM9200 196 CPU Address Line Row[10:0] Row[10:0] Row[10:0] Row[10:0] CPU Address Line Row[11:0] Row[11:0] ...
Page 197
... PIO controller to assign the SDRAM Controller pins to their peripheral function. If I/O lines of the SDRAM Controller are not used by the application, they can be used for other purposes by the PIO Controller. 1768I–ATARM–09-Jul- 8th Auto-refresh AT91RM9200 is met. MRD MRD ...
Page 198
... This interrupt may be ORed with other System Peripheral interrupt lines and is finally provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Controller). Using the SDRAM Controller interrupt requires the AIC to be programmed first. AT91RM9200 198 1768I–ATARM–09-Jul-09 ...
Page 199
... D[31:0] 1768I–ATARM–09-Jul-09 ) commands. For definition of these timing parameters, refer to the RCD col a col b col c col d col e Dna Dnb Dnc Dnd Dne AT91RM9200 ) commands and RP 208. This is described in Figure 19-3 col f col g col h col i col j col k Dnf Dng Dnh Dni ...
Page 200
... Figure 19-4. Read Burst, 32-bit SDRAM access SDCS SDCK A[12:0] Row n RAS CAS SDWE D[31:0] (Input) AT91RM9200 200 ) command, After a read command, additional wait states are generated to RCD 19.7.3 “SDRAMC Configuration Register” on page Figure 19-4 below CAS = 2 RCD col a ...