AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 127

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

16.3.5
16.3.6
1768I–ATARM–09-Jul-09
Misalignment Detector
Memory Controller Interrupt
The Memory Controller features a Misalignment Detector that checks the consistency of the
accesses.
For each access, regardless of the master, the size of access and the 0 and 1 bits of the
address bus are checked. If the type of access is a word (32-bit) and the 0 and 1 bits are not 0,
or if the type of the access is a half-word (16-bit) and the 0 bit is not 0, an abort is returned to the
master and the access is cancelled. Note that the accesses of the ARM processor when it is
fetching instructions are not checked.
The misalignments are generally due to software errors leading to wrong pointer handling.
These errors are particularly difficult to detect in the debug phase.
As the requested address is saved in the Abort Status and the address of the instruction gener-
ating the misalignment is saved in the Abort Link Register of the processor, detection and
correction of this kind of software error is simplified.
The Memory Controller itself does not generate any interrupt. However, as indicated in
16-1, the Memory Controller receives an interrupt signal from the External Bus Interface, which
might be activated in case of Refresh Error detected by the SDRAM Controller. This interrupt
signal just transits through the Memory Controller, which can neither enable/disable it nor return
its activity.
This Memory Controller interrupt signal is ORed with the other System Peripheral interrupt lines
(RTC, ST, DBGU, PMC) to provide the System Interrupt on Source 1 of the Advanced Interrupt
Controller.
AT91RM9200
Figure
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