AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 193

IC ARM9 MCU 208 PQFP

AT91RM9200-QI-002

Manufacturer Part Number
AT91RM9200-QI-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91RM9200-QI-002

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91RM9200-QI-002
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91RM9200-QI-002 SL383
Manufacturer:
Atmel
Quantity:
10 000
19. SDRAM Controller (SDRAMC)
19.1
1768I–ATARM–09-Jul-09
Overview
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing
the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges
from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit),
half-word (16-bit) and word (32-bit) accesses.
The SDRAM Controller supports a read or write burst length of one location. It does not
support byte Read/Write bursts or half-word write bursts. It keeps track of the active row
in each bank, thus maximizing SDRAM performance, e.g., the application may be placed
in one bank and data in the other banks. So as to optimize performance, it is advisable to
avoid accessing different rows in the same bank.
Features of the SDRAMC are:
• Numerous Configurations Supported
• Programming Facilities
• Energy-saving Capabilities
• Error Detection
• SDRAM Power-up Initialization by Software
• Latency is Set to Two Clocks (CAS Latency of 1, 3 Not Supported)
• Auto Precharge Command Not Used
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with Two or Four Internal Banks
– SDRAM with 16- or 32-bit Data Path
– Word, Half-word, Byte Access
– Automatic Page Break When Memory Boundary Has Been Reached
– Multibank Ping-pong Access
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Self-refresh and Low-power Modes Supported
– Refresh Error Interrupt
AT91RM9200
193

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