AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 601

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

36. Ethernet MAC (EMAC)
36.1
1768I–ATARM–09-Jul-09
Overview
The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model
between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange
between a host and a PHY layer according to Ethernet IEEE 802.3u data frame format. The
Ethernet MAC contains the required logic and transmit and receive FIFOs for DMA manage-
ment. In addition, it is interfaced through MDIO/MDC pins for PHY layer management.
The Ethernet MAC can transfer data in media-independent interface (MII) or reduced media-
independent interface (RMII) modes depending on the pinout configuration.
The aim of the reduced interface is to lower the pin count for a switch product that can be con-
nected to multiple PHY interfaces. The characteristics specific to RMII mode are:
The major features of the EMAC are:
• Single clock at 50 MHz frequency
• Reduction of required control pins
• Reduction of data paths to di-bit (2-bit wide) by doubling clock frequency
• 10 Mbits/sec. and 100 Mbits/sec. data capability
• Compatibility with IEEE Standard 802.3
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operation
• MII or RMII interface to the physical layer
• Register interface to address, status and control registers
• DMA interface
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Supports promiscuous mode where all valid frames are copied to memory
• Supports physical layer management through MDIO interface control of alarm and update
time/calendar data in
AT91RM9200
601