AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 271

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

23.4.7.2
23.4.7.3
1768I–ATARM–09-Jul-09
Processor Clock Source
Idle Mode
Peripheral Clock Controller
Processor Clock Controller
Figure 23-8. Master Clock Controller
The PMC features a Processor Clock Controller that implements the Idle Mode. The Processor
Clock can be enabled and disabled by writing the System Clock Enable (PMC_SCER) and Sys-
tem Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose)
can be read in the System Clock Status Register (PMC_SCSR).
The clock provided to the processor is determined by the Master Clock controller. On ARM7-
based systems, the Processor Clock source is directly the Master Clock.
On ARM9-based systems, the Processor Clock source might be 2, 3 or 4 times the Master
Clock. This ratio value is determined by programming the field MDIV of the Master Clock Regis-
ter (PMC_MCKR).
The Processor Clock is enabled after a reset and is automatically re-enabled by any enabled
interrupt. The Idle Mode is achieved by disabling the Processor Clock, which is automatically re-
enabled by any enabled fast or normal interrupt, or by the reset of the product.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The PMC controls the clocks of each embedded peripheral. The user can individually enable
and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable
(PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the periph-
eral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. When the clock is re-
enabled, the peripheral resumes action where it left off. The peripheral clocks are automatically
disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programmed operation before disabling the clock. This is to avoid data cor-
ruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and
PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number
corresponds to the interrupt source number assigned to the peripheral.
PLLA Clock
PLLB Clock
Main Clock
SLCK
CD
Master Clock
Prescaler
PRES
Master
Divider
MDIV
Clock
MCK
To the Processor
Clock Controller
MCK
To the Processor
Clock Controller
AT91RM9200
ARM9 Products
ARM7 Products
271