AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 375

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

28.5.1.2
28.5.1.3
28.5.1.4
1768I–ATARM–09-Jul-09
Variable Peripheral Select
Chip Selects
Clock Generation and Transfer Delays
Variable Peripheral Select is activated by setting bit PS to one. The PCS field in SPI_TDR is
used to select the destination peripheral. The data transfer characteristics are changed when
the selected peripheral changes, according to the associated chip select register.
The PCS field in the SPI_MR has no effect.
This option is only available when the SPI is programmed in Master Mode.
The Chip Select lines are driven by the SPI only if it is programmed in Master Mode. These lines
are used to select the destination peripheral. The PCSDEC field in SPI_MR (Mode Register)
selects one to four peripherals (PCSDEC = 0) or up to 15 peripherals (PCSDEC = 1).
If Variable Peripheral Select is active, the chip select signals are defined for each transfer in the
PCS field in SPI_TDR. Chip select signals can thus be defined independently for each transfer.
If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by the field
PCS in SPI_MR. If a transfer with a new peripheral is necessary, the software must wait until the
current transfer is completed, then change the value of PCS in SPI_MR before writing new data
in SPI_TDR.
The value on the NPCS pins at the end of each transfer can be read in the SPI_RDR (Receive
Data Register).
By default, all NPCS signals are high (equal to one) before and after each transfer.
The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock
divided by 32 (if DIV32 is set in the Mode Register) by a value between 4 and 510. The divisor is
defined in the SCBR field in each Chip Select Register. The transfer speed can thus be defined
independently for each chip select signal.
Figure 28-3
selects. Three delays can be programmed to modify the transfer waveforms:
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
• Delay between chip selects, programmable only once for all the chip selects by writing the
• Delay before SPCK, independently programmable for each chip select by writing the field
• Delay between consecutive transfers, independently programmable for each chip select by
field DLYBCS in the Mode Register. Allows insertion of a delay between release of one chip
select and before assertion of a new one.
DLYBS. Allows the start of SPCK to be delayed until after the chip select has been asserted.
writing the field DLYBCT. Allows insertion of a delay between two transfers occurring on the
same chip select
shows a chip select transfer change and consecutive transfers on the same chip
AT91RM9200
375