AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 43

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

11.5
11.5.1
11.5.2
1768I–ATARM–09-Jul-09
Memory Management Unit (MMU)
Domain
MMU Faults
The ARM920T processor implements an enhanced ARM architecture v4 MMU to provide trans-
lation and access permission checks for the instruction and data address ports of the
ARM9TDMI core. The MMU is controlled from a single set of two-level page tables stored in the
main memory, providing a single address and translation protection scheme. Independently,
instruction and data TLBs in the MMU can be locked and flushed.
Table 11-5.
A domain is a collection of sections and pages. The ARM920T supports 16 domains. Access to
the domains is controlled by the Domain Access Control register. For details, refer to
Register 3, Domain Access Control Register” on page
The MMU generates alignment faults, translation faults, domain faults and permission faults.
Alignment fault checking is not affected by whether the MMU is enabled or not.
The access controls of the MMU detect the conditions that produce these faults. If the fault is a
result of memory access, the MMU aborts the access and signals the fault to the CPU core.The
MMU stores the status and address fault in the FSR and FAR registers (only for faults generated
by data access).
The MMU does not store fault information about faults generated by an instruction fetch.
The memory system can abort during line fetches, memory accesses and translation table
access.
Mapping Name
Section
Large Page
Small Page
Tiny Page
Mapping Details
Mapping Size
1M byte
64K bytes
4K bytes
1K byte
Access Permission By
4 separated subpages
Section
4 separated subpages
Tiny Page
50.
Subpage Size
-
16K bytes
1K byte
-
AT91RM9200
“CP15
43