AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 39

IC ARM9 MCU 208 PQFP

AT91RM9200-QI-002

Manufacturer Part Number
AT91RM9200-QI-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91RM9200-QI-002

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91RM9200-QI-002
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91RM9200-QI-002 SL383
Manufacturer:
Atmel
Quantity:
10 000
Table 11-2.
11.3.6
1768I–ATARM–09-Jul-09
Mnemonic
SMULL
LDRSH
LDRSB
SMLAL
LDRBT
LDRH
LDRB
LDRT
MOV
CMP
EOR
MSR
SWP
MCR
ADD
SUB
RSB
AND
MUL
LDR
LDM
LDC
TST
BX
B
Thumb Instruction Set Overview
ARM Instruction Mnemonic List
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
Signed Long Multiply Accumulate
Move to Status Register
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Branch
Table 11-2
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
In Thumb mode, eight general-purpose registers are available, R0 to R7, that are the same
physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also
access the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
gives the ARM instruction mnemonic list.
Mnemonic
UMULL
UMLAL
STRBT
SWPB
STRH
STRB
STRT
MVN
CMN
ORR
MRS
MRC
CDP
ADC
SBC
RSC
TEQ
MLA
STR
STM
STC
SWI
BIC
BL
Operation
Coprocessor Data Processing
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply Accumulate
Move From Status Register
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
AT91RM9200
39

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