AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 119

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

15.1.3
Table 15-2.
1768I–ATARM–09-Jul-09
Feature
Power Supply Monitoring
Reset Active Timeout
Period
Manual Reset Command
Required Features for the Reset Controller
Reset Controller Functions Synthesis
The NTRST control pin initializes the selected TAP controller. The TAP controller involved in this
reset is determined according to the initial logical state applied on the JTAGSEL pin after the last
valid NRST.
In Boundary Scan Mode, after a NTRST assertion, the IDCODE instruction is set onto the output
of the instruction register in the Test-Logic-Reset controller state.
Otherwise, in ICE Mode, the reset action is as follows:
•
•
In either Boundary Scan or ICE Mode a reset can be performed from the same or different cir-
cuitry, as shown in
Figure 15-3. Separate or Common Reset Management
Notes:
In order to benefit the most regarding the separation of NRST and NTRST during the Debug
phase of development, the user must independently manage both signals as shown in example
(1) of
together during production as shown in example (2) of
The following table presents the features required of a reset controller in order to obtain an opti-
mal system with the AT91RM9200 processor.
Description
Overlaps the transient state of the system during power-up/down and brownout.
Overlaps the start-up time of the boot-up oscillator by holding the reset signal during this delay.
Asserts the reset signal from a logic command and holds the reset signal with a shorter delay than that
of the “Reset Active Timeout Period”.
The core exits from Debug Mode.
The IDCORE instruction is requested.
Figure 15-3
1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
Controller
Controller
Reset
Reset
above. However, once Debug is completed, both signals are easily managed
Figure 15-3
NTRST
NRST
AT91RM9200
below, upon system reset at power-up or upon user request.
(1)
Figure 15-3
Controller
Reset
above.
AT91RM9200
AT91RM9200
NTRST
NRST
(2)
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