AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 239

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

22. Advanced Interrupt Controller (AIC)
22.1
1768I–ATARM–09-Jul-09
Overview
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored
interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to sub-
stantially reduce the software and real-time overhead in handling internal and external
interrupts.
The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs
of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external inter-
rupts coming from the product's pins.
The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus
permitting higher priority interrupts to be serviced even if a lower priority interrupt is being
treated.
Internal interrupt sources can be programmed to be level sensitive or edge triggered. External
interrupt sources can be programmed to be positive-edge or negative-edge triggered or high-
level or low-level sensitive.
Important Features of the AIC are:
• Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM Processor
• Thirty-two Individually Maskable and Vectored Interrupt Sources
• 8-level Priority Controller
• Vectoring
• Protect Mode
• General Interrupt Mask
– Source 0 is Reserved for the Fast Interrupt Input (FIQ)
– Source 1 is Reserved for System Peripherals (ST, RTC, PMC, DBGU…)
– Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts or
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
– Drives the Normal Interrupt of the Processor
– Handles Priority of the Interrupt Sources 1 to 31
– Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per Interrupt Source
– Interrupt Vector Register Reads the Corresponding Current Interrupt Vector
– Easy Debugging by Preventing Automatic Operations when Protect ModeIs Are
– Provides Processor Synchronization on Events Without Triggering an Interrupt
External Interrupts
External Sources
Enabled
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