AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 371

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

28. Serial Peripheral Interface (SPI)
28.1
1768I–ATARM–09-Jul-09
Overview
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also allows communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs.
During a data transfer, one SPI system acts as the master that controls the data flow, while the
other system acts as the slave, having data shifted into and out of it by the master. Different
CPUs can take turn being masters (Multiple Master Protocol versus Single Master Protocol
where one CPU is always the master while all of the others are always slaves), and one master
may simultaneously shift data into multiple slaves. However, only one slave may drive its output
to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
The main features of the SPI are:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
• Supports Communication with Serial External Devices
• Master or Slave Serial Peripheral Bus Interface
• Connection to PDC Channel Capabilities Optimizes Data Transfers
into the input(s) of the slave(s).
of the master. There may be no more than one slave transmitting data during any particular
transfer.
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once
for each bit that is transmitted.
– 4 Chip Selects with External Decoder Support Allow Communication with Up to 15
– Serial Memories, such as DataFlash and 3-wire EEPROMs
– Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
– External Co-processors
– 8- to 16-bit Programmable Data Length Per Chip Select
– Programmable Phase and Polarity Per Chip Select
– Programmable Transfer Delays Between Consecutive Transfers and Between Clock
– Programmable Delay Between Consecutive Transfers
– Selectable Mode Fault Detection
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
Peripherals
Sensors
and Data Per Chip Select
AT91RM9200
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