AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 473

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

31.8.4
Register Name:
Access Type:
• DATLEN: Data Length
0x0 is not supported. The value of DATLEN can be set between 0x1 and 0x1F.
The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the
Receiver.
If DATLEN is less than or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are
transferred. For any other value, 32-bit words are transferred.
• LOOP: Loop Mode
0: Normal operating mode.
1: RD is driven by TD, RF is driven by TF and TK drives RK.
• MSBF: Most Significant Bit First
0: The lowest significant bit of the data register is sampled first in the bit stream.
1: The most significant bit of the data register is sampled first in the bit stream.
• DATNB: Data Number per Frame
This field defines the number of data words to be received after each transfer start. If 0, only 1 data word is transferred. Up
to 16 data words can be transferred.
• FSLEN: Receive Frame Sync Length
This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive
Sync Data Register. Only when FSOS is set on negative or positive pulse.
• FSOS: Receive Frame Sync Output Selection
1768I–ATARM–09-Jul-09
MSBF
0x6-0x7
31
23
15
FSOS
–
–
–
7
0x0
0x1
0x2
0x3
0x4
0x5
SSC Receive Frame Mode Register
Selected Receive Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
30
22
14
SSC_RFMR
Read/Write
–
–
6
–
FSOS
LOOP
29
21
13
–
–
5
28
20
12
–
–
4
27
19
11
–
3
DATLEN
26
18
10
–
2
FSLEN
DATNB
AT91RM9200
25
17
–
9
1
Undefined
Input-only
RF pin
Output
Output
Output
Output
Output
FSEDGE
24
16
8
0
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