AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 58
AT91RM9200-QI-002
Manufacturer Part Number
AT91RM9200-QI-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-QI-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91RM9200-QI-002 SL383
Manufacturer:
Atmel
Quantity:
10 000
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11.7.13
Access: Read/Write
The CP15 Register 13, or Fast Context Switch Extension (FCSE) Process Identifier (PID) Register, is set to 0x0 on reset.
Reading from CP15 Register 13 returns the FCSE PID value.
Writing to CP15 Register 13 sets the FCSE PID.
The FCSE PID sets the mapping between the ARM9TDMI and the MMU of the cache memories.
The addresses issued by the ARM9TDMI are in the range of 0 to 32 Mbytes and are translated via the FCSE PID.
• FCSEPID[31:25]: FCSE PID
The FCSE PID modifies the behavior of the of the ARM920T memory system. This modification allows multiple programs to
run on the ARM.
The 4-GB virtual address is divided into 128 process blocks of 32 Mbytes each. Each process block can contain a program
that has been compiled to use the address range 0x00000000 to 0x01FFFFFF. For each i = 0 to 127 process blocks, i runs
from address i*0x20000000 to address i*0x20000000 + 0x01FFFFFF.
For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C.
The non-defined bits should be zero when written and are unpredictable when read.
11.7.14
Any access (Read or Write) of these registers causes unpredictable behavior.
11.7.15
CP15 Register 15, or Test Configuration Register, is used for test purposed. Any access (write or read) to this register
causes unpredictable behavior.
58
31
23
15
7
-
-
-
AT91RM9200
CP15 Register 13, FCSE PID Register
CP15 Register 14, Reserved
CP15 Register 15, Test Configuration Register
30
22
14
6
-
-
-
29
21
13
5
-
-
-
FCSEPID
28
20
12
4
-
-
-
27
19
11
3
-
-
-
26
18
10
2
-
-
-
25
17
9
1
-
-
-
1768I–ATARM–09-Jul-09
24
16
8
0
-
-
-
-
D
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