AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 200

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

19.6.2
Figure 19-4. Read Burst, 32-bit SDRAM access
200
AT91RM9200
SDRAM Controller Read Cycle
D[31:0]
A[12:0]
SDWE
SDCS
(Input)
SDCK
RAS
CAS
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the transfer type signal provided by the master requesting the access. If
the next access is a sequential read access, reading to the SDRAM device is carried out. If the
next access is a sequential read access, but the current access is to a boundary page, or if the
next access is in another row, then the SDRAM Controller generates a precharge command,
activates the new row and initiates a read command. To comply with SDRAM timing parameters,
an additional clock cycle is inserted between the precharge/active (t
active/read (t
comply with cas latency. The SDRAM Controller supports a cas latency of two. For definition of
these timing parameters, refer to
described in
Row n
t
RCD
Figure 19-4
RCD
= 3
) command, After a read command, additional wait states are generated to
col a
below.
CAS = 2
col b
Dna
19.7.3 “SDRAMC Configuration Register” on page
col c
Dnb
col d
Dnc
col e
Dnd
col f
Dne
Dnf
RP
) command and the
1768I–ATARM–09-Jul-09
208. This is