AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 294

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

24.3
24.4
24.4.1
24.4.2
24.5
24.5.1
24.5.2
294
Application Block Diagram
Product Dependencies
Functional Description
AT91RM9200
Power Management
Interrupt Sources
System Timer Clock
Period Interval Timer (PIT)
Figure 24-2. Application Block Diagram
The System Timer is continuously clocked at 32768 Hz. The power management controller has
no effect on the system timer behavior.
The System Timer interrupt is generally connected to the source 1 of the Advanced Interrupt
Controller. This interrupt line is the result of the OR-wiring of the system peripheral interrupt lines
(System Timer, Real Time Clock, Power Management Controller, Memory Controller). When a
system interrupt happens, the service routine must first determine the cause of the interrupt.
This is accomplished by reading successively the status registers of the above mentioned sys-
tem peripherals.
The System Timer uses only the SLCK clock so that it is capable to provide periodic, watchdog,
second change or alarm interrupt even if the Power Management Controller is programmed to
put the product in Slow Clock Mode. If the product has the capability to back up the Slow Clock
oscillator and the System Timer, the System Timer can continue to operate.
The Period Interval Timer can be used to provide periodic interrupts for use by operating sys-
tems. The reset value of the PIT is 0 corresponding to the maximum value. It is built around a
16-bit down counter, which is preloaded by a value programmed in ST_PIMR (Period Interval
Mode Register). When the PIT counter reaches 0, the bit PITS is set in ST_SR (Status Regis-
ter), and an interrupt is generated if it is enabled.
The counter is then automatically reloaded and restarted. Writing to the ST_PIMR at any time
immediately reloads and restarts the down counter with the new programmed value.
Warning: If ST_PIMR is programmed with a period less or equal to the current MCK period, the
update of the PITS status bit and its associated interrupt generation are unpredictable.
OS or RTOS
Scheduler
PIT
Date, Time
and Alarm
Manager
RTT
System Survey
Manager
WDT
1768I–ATARM–09-Jul-09