AT91RM9200-QI-002 Atmel, AT91RM9200-QI-002 Datasheet - Page 488

• Manufacturer Part Number: AT91RM9200-QI-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

32.5.1.3
488
AT91RM9200
Clock Control
This selection is made by the TCCLKS bits in the TC Channel Mode Register (Capture Mode).
The selected clock can be inverted with the CLKI bit in TC_CMR (Capture Mode). This allows
counting on the opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST
parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note:
Figure 32-2. Clock Selection
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See
• External clock signals: XC0, XC1 or XC2
• The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
• The clock can also be started or stopped: a trigger (software, synchro, external or compare)
commands in the Control Register. In Capture Mode it can be disabled by an RB load event if
LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare
event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no
effect: only a CLKEN command in the Control Register can re-enable the clock. When the
clock is enabled, the CLKSTA bit is set in the Status Register.
always starts the clock. The clock can be stopped by an RB load event in Capture Mode
(LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in
TC_CMR). The start and the stop commands have effect only if the clock is enabled.
In all cases, if an external clock is used, the duration of each of its levels must be longer than the
master clock period. The external clock frequency must be at least 2.5 times lower than the mas-
ter clock
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Figure
32-3.
1
TCCLKS
BURST
CLKI
Selected
Clock
1768I–ATARM–09-Jul-09