HD6432621 Hitachi, HD6432621 Datasheet - Page 978

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
TIOR0L—Timer I/O Control Register 0L
934
Bit
Initial value
Read/Write
Note: When TGR0C or TGR0D is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
:
:
:
TGR0D I/O control
Note: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the
0 0
1
IOD3
R/W
7
0
1 0 0
0
1
0 0
1 0
1 0
0 0 TGR0D
1 *
*
TCNT1 count clock, this setting is invalid and input capture is not generated.
1
1
1
1
1
*
TGR0D
is output
compare
register
is input
capture
register
IOD2
R/W
TGR0C I/O control
6
0
0 0
1
1 0 0
0
1
0 0
1 0
1 0
0 0 TGR0C
1 *
*
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
IOD1
1
1
1
1
1
*
R/W
5
0
TGR0C
is output
compare
register
is input
capture
register
IOD0
R/W
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
4
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
H'FF13
IOC3
R/W
3
0
*1
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
IOC2
R/W
2
0
*: Don’t care
IOC1
R/W
1
0
*: Don’t care
IOC0
R/W
0
0
TPU0

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