HD6432621 Hitachi, HD6432621 Datasheet - Page 27

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Section
B.2 Functions
C.4 Port A Block
Diagrams
Figure C-4 (c) Port A
Block Diagram (Pin
PA2)
Page
870
871
872
873
874
875
881
930
979
1000
Description
MC10—Message Control
(Incorrect) x = 0
MC11—Message Control
(Incorrect) x = 0
MC12—Message Control
(Incorrect) x = 0
MC13—Message Control
(Incorrect) x = 0
MC14—Message Control
(Incorrect) x = 0
MC15—Message Control
(Incorrect) x = 0
SCKCR—System Clock Control Register
Generator, Power-Down
Note amended
Note: * Subclock functions (subactive mode, subsleep mode, and watch
PFDR—Port F Data Register
ADDRA—A/D Data Register A
ADDRB—A/D Data Register B
ADDRC—A/D Data Register C
ADDRD—A/D Data Register D
Note added
Note: The upper byte can be read directly, but for the lower byte, data
(Incorrect) SCK input enable, SCK input
(Correct)
Bit
Initial value
Read/Write
transfer is performed via a temporary register (TEMP). For details,
see section 16.3, Interface to Bus Master.
mode) and direct transition are not available in the H8S/2623 Series,
but are available in the H8S/2626 Series.
:
:
:
RxD input enable, RxD input
R/W
7
0
PF6DR
R/W
(Correct) x = 10
(Correct) x = 11
(Correct) x = 12
(Correct) x = 13
(Correct) x = 14
(Correct) x = 15
6
0
Stores output data for port F pins (PF6 to PF0)
PF5DR
H'F870
H'F878
H'F880
H'F888
H'F890
H'F898
R/W
5
0
H'FF0E
H'FF90
H'FF92
H'FF94
H'FF96
PF4DR
R/W
4
0
HCAN
HCAN
HCAN
HCAN
HCAN
HCAN
H'FDE6
Port F
PF3DR
R/W
A/D Converter
A/D Converter
A/D Converter
A/D Converter
3
0
PF2DR
R/W
2
0
Clock Pulse
PF1DR
R/W
1
0
PF0DR
R/W
0
0

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