HD6432621 Hitachi, HD6432621 Datasheet - Page 602

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Table 15-3 BCR Register Value Setting Ranges
Name
Time segment 1
Time segment 2
Baud rate prescaler
Sample point
Re-synchronization jump width
b. Value Setting Ranges
The following formula is used to calculate the baud rate.
Example: With a 1 Mb/s baud rate and a 20 MHz input clock:
558
The bit width consists of the total of the settable Time Quanta (TQ). TQ (number of system
clocks) is determined by the baud rate prescaler (BRP).
The value of SJW is stipulated in the CAN specifications.
The minimum value of TSEG1 is stipulated in the CAN specifications.
The minimum value of TSEG2 is stipulated in the CAN specifications.
TQ =
3 SJW
TSEG1 TSEG2
TSEG2 SJW
Bit rate [b/s] =
Note: f
1 Mb/s =
2 (BRP + 1)
The BCR values are used for BRP, TSEG1, and TSEG2.
CLK
2
0
=
f
CLK
(0 + 1)
(system clock)
2
20 MHz
(BRP + 1)
(3 + 4 + 3)
Abbreviation
TSEG1
TSEG2
BRP
SAM
SJW
(3 + TSEG1 + TSEG2)
f
CLK
Min. Value
B'0000
B'000
B'000000
B'0
B'00
Max. Value
B'1111
B'111
B'111111
B'1
B'11

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