HD6432621 Hitachi, HD6432621 Datasheet - Page 226

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

8.2
8.2.1
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
SM1
0
1
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
DM1
0
1
182
R/W
Bit
Initial value
Register Descriptions
DTC Mode Register A (MRA)
Bit 6
SM0
—
0
1
Bit 4
DM0
—
0
1
:
:
:
Unde-
SM1
fined
—
7
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Unde-
fined
SM0
—
6
Unde-
DM1
fined
—
5
Unde-
DM0
fined
—
4
Unde-
MD1
fined
—
3
Unde-
MD0
fined
—
2
Unde-
fined
DTS
—
1
Unde-
fined
Sz
—
0