HD6432621 Hitachi, HD6432621 Datasheet - Page 752
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
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21B.2 Register Descriptions
21B.2.1 Standby Control Register (SBYCR)
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by
executing the SLEEP instruction, the operating mode is determined in combination with other
control bits.
Note that the value of the SSBY bit does not change even when shifting between modes using
interrupts.
Bit 7
SSBY
0
1
708
Bit
Initial value :
R/W
Description
Shifts to sleep mode when the SLEEP instruction is executed in high-speed
mode or medium-speed mode.
Shifts to sub-sleep mode when the SLEEP instruction is executed in
sub-active mode.
Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP
instruction is executed in high-speed mode or medium-speed mode.
Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in
sub-active mode.
:
:
SSBY
R/W
7
0
STS2
R/W
6
0
STS1
R/W
5
0
STS0
R/W
4
0
OPE
R/W
3
1
—
—
2
0
—
—
1
0
(Initial value)
—
—
0
0
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