HD6432621 Hitachi, HD6432621 Datasheet - Page 764

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
21B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the
oscillation stabilization time).
Table 21B-5 shows the standby times for different operating frequencies and settings of bits STS2
to STS0.
Table 21B-5 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time
0
1
Note: * Do not use this setting.
Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore,
the standby time should be set to a value of 2 ms or greater.
720
Clearing with the RES pin
When the RES pin is driven Low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held
Low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset
exception handling.
Clearing with the STBY pin
When the STBY pin is driven Low, a transition is made to hardware standby mode.
: Recommended time setting
0
1
0
1
0
1
0
1
0
1
0
1
8192 states
16384 states
32768 states
65536 states
131072 states
262144 states
Reserved
16 states*
20
MHz
0.41 0.51 0.68 0.8
0.82 1.0
1.6
3.3
6.6
0.8
13.1 16.4 21.8 26.2 32.8 43.6 65.6
16
MHz
2.0
4.1
1.0
8.2
12
MHz
1.3
2.7
5.5
1.3
10.9 13.1 16.4 21.8 32.8
10
MHz
1.6
3.3
6.6
1.6
8
MHz
1.0
2.0
4.1
2.0
8.2
6
MHz
1.3
2.7
5.5
1.7
10.9 16.4
4
MHz Unit
2.0
4.1
4.0
8.2
ms
µs

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