HD6432621 Hitachi, HD6432621 Datasheet - Page 722

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master
clock.
Bit 2
SCK2
0
1
20.2.2
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized by a
manual reset or in software standby mode.
Bits 7 to 2—Reserved: The function of these bits differs between the H8S/2623 Series and
H8S/2626 Series.
For details see sections 21A.2.3, 21B.2.3, Low-Power Control Register (LPWRCR).
Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the
frequency multiplication factor of the PLL circuit.
Bit 1
STC1
0
1
678
Bit
Initial value
Read/Write
Bit 1
SCK1
0
1
0
1
Low-Power Control Register (LPWRCR)
Bit 0
STC0
0
1
0
1
DTON
R/W
Bit 0
SCK0
0
1
0
1
0
1
—
7
0
Description
Setting prohibited
1
2
4
LSON
R/W
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
6
0
NESEL
R/W
5
0
SUBSTP
R/W
4
0
RFCUT
R/W
3
0
R/W
—
2
0
STC1
R/W
1
0
(Initial value)
(Initial value)
STC0
R/W
0
0