HD6432621 Hitachi, HD6432621 Datasheet - Page 471

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 13.2.8, Bit Rate Register (BRR).
Bit 1
CKS1
0
1
13.2.6
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE
0
1
Note: TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then
Bit
Initial value
R/W
clearing it to 0, or clearing the TIE bit to 0.
Serial Control Register (SCR)
Bit 0
CKS0
0
1
0
1
Description
Transmit data empty interrupt (TXI) requests disabled
Transmit data empty interrupt (TXI) requests enabled
:
:
:
R/W
TIE
7
0
Description
ø clock
ø/4 clock
ø/16 clock
ø/64 clock
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0
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