HD6432621 Hitachi, HD6432621 Datasheet - Page 277

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

9.5.2
Table 9-6 shows the port A register configuration.
Table 9-6
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Notes: *1 Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read.
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 and 6 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address
output pins retain their output state or become high-impedance when a transition is made to
software standby mode.
Bit
Initial value :
R/W
Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA5DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
*2 Value of bits 3 to 0.
Register Configuration
Port A Registers
:
:
Undefined Undefined
—
—
7
—
—
6
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
PA5DDR * PA4DDR * PA3DDR
W
5
0
W
4
0
R/W
W
R/W
R
R/W
R/W
W
3
0
Initial Value*
H'0
H'0
Undefined
H'0
H'0
PA2DDR
W
2
0
PA1DDR
2
W
1
0
Address*
H'FE39
H'FF09
H'FFB9
H'FE40
H'FE47
PA0DDR
W
0
0
1
233