HD6432621 Hitachi, HD6432621 Datasheet - Page 623

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

15.5
1. Reset
2. HCAN sleep mode
3. Interrupts
The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All
the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data
(MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message
data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization
must always be carried out after a reset or a transition to hardware standby mode or software
standby mode. Also, the reset interrupt flag (IRR0) is always set after reset input or recovery
from software standby mode. As this bit cannot be masked in the interrupt mask register
(IMR), if HCAN interrupts are set as enabled by the interrupt controller without this flag
having been cleared, an HCAN interrupt will be initiated immediately. IRR0 must therefore be
cleared during initialization.
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation
in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode
release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in
sleep mode.
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8.2.1) is
not set by reception completion, transmission completion, or transmission cancellation for the
set mailboxes.
H8S/2626 Series or
H8S/2623 Series
Usage Notes
HRxD
HTxD
Figure 15-14 High-Speed Interface Using PCA82C250
No connection
PCA82C250
RS
RxD
TxD
Vref
CANH
CANL
GND
Vcc
Vcc
124
124
CAN bus
579