HD6432621 Hitachi, HD6432621 Datasheet - Page 746

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

21A.7.2 Hardware Standby Mode Timing
Figure 21A-4 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,
waiting for the oscillation stabilization time, then changing the RES pin from low to high.
21A.8 ø Clock Output Disabling Function
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,
and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.
Table 21A-5 shows the state of the ø pin in each processing state.
Table 21A-5 ø Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby
Sleep mode
High-speed mode, medium-speed
mode
702
Oscillator
RES
STBY
Figure 21A-4 Hardware Standby Mode Timing
0
—
High impedance
High impedance
High impedance
High impedance
1
0
High impedance
Fixed high
ø output
ø output
Oscillation
stabilization
time
1
1
High impedance
Fixed high
Fixed high
Fixed high
exception
handling
Reset