HD6432621 Hitachi, HD6432621 Datasheet - Page 545
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
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The operation sequence is as follows.
[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start
[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data
[4] The receiving station carries out a parity check.
[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data
(2) Block Transfer Mode
The operation sequence in block transfer mode is as follows.
[1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pull-
[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start
[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data
[4] After reception, a parity error check is carried out, but an error signal is not output even if an
[5] The transmitting station proceeds to transmit the next data frame.
up resistor.
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
line is pulled high with a pull-up resistor.
If there is no parity error and the data is received normally, the receiving station waits for
reception of the next data.
If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)
to request retransmission of the data. After outputting the error signal for the prescribed length
of time, the receiving station places the signal line in the high-impedance state again. The
signal line is pulled high again by a pull-up resistor.
frame.
If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous
data.
up resistor.
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
line is pulled high with a pull-up resistor.
error has occurred. When an error occurs reception cannot be continued, so the error flag
should be cleared to 0 before the parity bit of the next frame is received.
501
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