HD6432621 Hitachi, HD6432621 Datasheet - Page 898

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
854
IRR
Bit
Initial value
Read/Write
Note: * Can only be written with 1 for flag clearing.
:
:
:
7
0
6
0
5
0
Bus operation interrupt flag
R/(W)*
IRR12
0
1
4
0
CAN bus idle state
[Clearing condition]
Writing 1
CAN bus operation in HCAN sleep mode
[Setting condition]
Bus operation (dominant bit detection) in HCAN sleep mode
Unread interrupt flag
0
1
[Clearing condition]
Clearing of all bits in UMSR (unread message
status register)
Unread message overwrite
[Setting condition]
When UMSR (unread message status register)
is set
3
0
Mailbox empty interrupt flag
0
1
[Clearing condition]
Writing 1
Transmit message has been transmitted
or aborted, and new message can be
stored
[Setting condition]
When TXPR (transmit wait register) is
cleared by completion of transmission or
completion of transmission abort
2
0
IRR9
R
1
0
R/(W)*
IRR8
0
0

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