HD6432621 Hitachi, HD6432621 Datasheet - Page 946

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCR3—Timer Control Register 3
902
Bit
Initial value
Read/Write
Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
Counter clear
0
1
0
1
0
1
*2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
0
1
0
1
0
1
0
1
:
:
:
buffer register setting has priority, and compare match/input capture does not occur.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
TCNT cleared by TGRD compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
CCLR2
R/W
7
0
CCLR1
R/W
6
0
Note: Internal clock edge selection is valid when the
Input clock edge select
CCLR0
0
1
R/W
5
0
—
0
1
Timer prescaler
input clock is ø/4 or slower. This setting is ignored
if is ø/1 is selected as the input clock.
0
1
Count at rising edge
Count at falling edge
Count at both edges
CKEG1
0
1
0
1
R/W
4
0
0
1
0
1
0
1
0
1
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
Internal clock: counts on ø/1024
Internal clock: counts on ø/256
Internal clock: counts on ø/4096
H'FE80
CKEG0
R/W
3
0
TPSC2
*2
*2
R/W
*1
*1
2
0
TPSC1
R/W
1
0
TPSC0
R/W
0
0
TPU3