HD6432621 Hitachi, HD6432621 Datasheet - Page 192

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is
used for an external write cycle.
Bit 1
WDBE
0
1
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
0
1
7.2.6
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous
state in software standby mode.
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bit 5—BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin. For
details, see section 12.2.4, Pin Function Control Register (PFCR).
Bit 4—Reserved: Only 0 should be written to this bit.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or
disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When
a pin is enabled for address output, the address is output regardless of the corresponding DDR
setting. When a pin is disabled for address output, it becomes an output port when the
corresponding DDR bit is set to 1.
148
Bit
Initial value
R/W
Pin Function Control Register (PFCR)
Description
Write data buffer function not used
Write data buffer function used
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
Wait input by WAIT pin enabled
:
:
:
R/W
—
7
0
R/W
—
6
0
BUZZE
R/W
5
0
R/W
—
4
0
R/W
AE3
1/0
3
R/W
AE2
1/0
2
R/W
AE1
1
0
(Initial value)
(Initial value)
AE0
R/W
1/0
0