HD6432621 Hitachi, HD6432621 Datasheet - Page 142

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
5.2
5.2.1
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control
Register (SYSCR).
SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5
INTM1
0
1
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
0
1
98
Bit
Initial value
R/W
Register Descriptions
System Control Register (SYSCR)
Bit 4
INTM0
0
1
0
1
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
:
:
:
MACS
R/W
Interrupt
Control Mode
0
2
7
0
6
0
INTM1
Description
Interrupts are controlled by I bit
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
R/W
5
0
INTM0
R/W
4
0
NMIEG
R/W
3
0
R/W
2
0
1
0
(Initial value)
(Initial value)
RAME
R/W
0
1

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