HD6432621 Hitachi, HD6432621 Datasheet - Page 619

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is
delayed until the bus becomes idle.
Either of the following methods of clearing HCAN sleep mode can be selected by making a setting
in the MCR7 bit.
1. Clearing by software
2. Clearing by CAN bus operation
Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus
communication is enabled again.
Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the
CAN bus performs an operation and this change is detected. In this case, the first message is not
received in the mailbox, and normal reception starts from the next message. When a change is
detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in
the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR)
is set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
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