HD6432621 Hitachi, HD6432621 Datasheet - Page 929

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

LPWRCR—Low-Power Control Register
Bit
Initial value
Read/Write
:
:
:
Direct transfer ON flag
Notes: This bit is valid only in the H8S/2626 Series; in the H8S/2623 Series, 0 must be written to this bit.
0
1
DTON
• When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
• When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep
• When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
• When the SLEEP command is executed in sub-active mode, operation transfers directly to high-
R/W
transfers to sleep mode, software standby mode, or watch mode*
mode or watch mode
transfers directly to sub-active mode, or transfers to sleep mode or software standby mode
speed mode or transfers to sub-sleep mode
7
0
* Always select high-speed mode when transferring to watch mode or sub-active mode.
Notes: This bit is valid only in the H8S/2626 Series; in the H8S/2623 Series, 0 must be written to this bit.
Low-speed ON flag
0
1
LSON
• When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
• When the SLEEP command is executed in sub-active mode, operation transfers to watch mode,
• Operation transfers to high-speed mode after watch mode is canceled
• When the SLEEP command is executed in high-speed mode, operation transfers to watch mode
• When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep
• Operation transfers to sub-active mode immediately watch mode is canceled
R/W
transfers to sleep mode, software standby mode, or watch mode*
or directly to high-speed mode
or sub-active mode
mode or watch mode
6
0
* Always select high-speed mode when transferring to watch mode or sub-active mode.
NESEL
R/W
Noise elimination sampling frequency select
Note: This bit is valid only in the H8S/2626 Series; in the
5
0
0 Sampling uses ø/32 clock
1
Sampling uses ø/4 clock
H8S/2623 Series, 0 must be written to this bit.
SUBSTP
R/W
Subclock enable
Note: This bit is valid only in the H8S/2626 Series; in the
4
0
0 Subclock generation enabled
1
Subclock generation disabled
H8S/2623 Series, 0 must be written to this bit.
H'FDEC
RFCUT
R/W
Oscillator circuit feedback resistor control bit
0 Feedback resistor ON when main clock operating;
1
3
0
OFF when not operation
Feedback resistor OFF
Frequency multiplier
Note: A system clock frequency multiplied
R/W
STC1
—
2
0
0
1
by the multiplication factor (STC1
and STC0) should not exceed the
maximum operating frequency
defined in section 22 Electrical
Characteristics.
Clock Pulse Generator
STC0
0
1
0
1
STC1
R/W
1
0
Do not set
1 (initial value)
2
4
STC0
R/W
0
0
885