HD6432621 Hitachi, HD6432621 Datasheet - Page 975

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCR0—Timer Control Register 0
Bit
Initial value
Read/Write
Counter clear
Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
0
1
0
1
0
1
:
:
:
*2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because
0
1
0
1
0
1
0
1
the buffer register setting has priority, and compare match/input capture does not
occur.
CCLR2
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
TCNT cleared by TGRD compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
R/W
7
0
CCLR1
R/W
6
0
Input clock edge select
Note: Internal clock edge selection is valid when the input
0
1
CCLR0
—
R/W
0
1
5
0
clock is ø/4 or slower. This setting is ignored if is ø/1 is
selected as the input clock.
Count at rising edge
Count at falling edge
Count at both edges
Time prescaler
0
1
CKEG1
0
1
0
1
R/W
4
0
0
1
0
1
0
1
0
1
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
H'FF10
CKEG0
R/W
3
0
TPSC2
R/W
*2
*2
2
0
*1
*1
TPSC1
R/W
1
0
TPSC0
R/W
0
0
TPU0
931